liquidio CN23XX: HW config for VF support
Adds support for configuring HW for creating VFs. Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raghu Vatsavayi
David S. Miller
parent
3418c6810e
commit
d13520c7ca
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@ -40,11 +40,6 @@
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*/
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#define CN23XX_INPUT_JABBER 64600
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#define LIOLUT_RING_DISTRIBUTION 9
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const int liolut_num_vfs_to_rings_per_vf[LIOLUT_RING_DISTRIBUTION] = {
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0, 8, 4, 2, 2, 2, 1, 1, 1
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};
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void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct)
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{
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int i = 0;
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@ -309,9 +304,10 @@ u32 cn23xx_pf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us)
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static void cn23xx_setup_global_mac_regs(struct octeon_device *oct)
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{
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u64 reg_val;
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u16 mac_no = oct->pcie_port;
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u16 pf_num = oct->pf_num;
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u64 reg_val;
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u64 temp;
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/* programming SRN and TRS for each MAC(0..3) */
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@ -333,6 +329,14 @@ static void cn23xx_setup_global_mac_regs(struct octeon_device *oct)
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/* setting TRS <23:16> */
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reg_val = reg_val |
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(oct->sriov_info.trs << CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS);
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/* setting RPVF <39:32> */
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temp = oct->sriov_info.rings_per_vf & 0xff;
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reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS);
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/* setting NVFS <55:48> */
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temp = oct->sriov_info.max_vfs & 0xff;
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reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS);
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/* write these settings to MAC register */
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octeon_write_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num),
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reg_val);
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@ -399,11 +403,12 @@ static int cn23xx_reset_io_queues(struct octeon_device *oct)
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static int cn23xx_pf_setup_global_input_regs(struct octeon_device *oct)
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{
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struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
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struct octeon_instr_queue *iq;
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u64 intr_threshold, reg_val;
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u32 q_no, ern, srn;
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u64 pf_num;
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u64 intr_threshold, reg_val;
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struct octeon_instr_queue *iq;
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struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
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u64 vf_num;
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pf_num = oct->pf_num;
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@ -420,6 +425,16 @@ static int cn23xx_pf_setup_global_input_regs(struct octeon_device *oct)
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*/
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for (q_no = 0; q_no < ern; q_no++) {
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reg_val = oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;
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/* for VF assigned queues. */
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if (q_no < oct->sriov_info.pf_srn) {
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vf_num = q_no / oct->sriov_info.rings_per_vf;
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vf_num += 1; /* VF1, VF2,........ */
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} else {
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vf_num = 0;
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}
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reg_val |= vf_num << CN23XX_PKT_INPUT_CTL_VF_NUM_POS;
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reg_val |= pf_num << CN23XX_PKT_INPUT_CTL_PF_NUM_POS;
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octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
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@ -1048,50 +1063,59 @@ static void cn23xx_setup_reg_address(struct octeon_device *oct)
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static int cn23xx_sriov_config(struct octeon_device *oct)
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{
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u32 total_rings;
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struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
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/* num_vfs is already filled for us */
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u32 max_rings, total_rings, max_vfs, rings_per_vf;
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u32 pf_srn, num_pf_rings;
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u32 max_possible_vfs;
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cn23xx->conf =
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(struct octeon_config *)oct_get_config_info(oct, LIO_23XX);
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(struct octeon_config *)oct_get_config_info(oct, LIO_23XX);
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switch (oct->rev_id) {
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case OCTEON_CN23XX_REV_1_0:
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total_rings = CN23XX_MAX_RINGS_PER_PF_PASS_1_0;
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max_rings = CN23XX_MAX_RINGS_PER_PF_PASS_1_0;
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max_possible_vfs = CN23XX_MAX_VFS_PER_PF_PASS_1_0;
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break;
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case OCTEON_CN23XX_REV_1_1:
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total_rings = CN23XX_MAX_RINGS_PER_PF_PASS_1_1;
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max_rings = CN23XX_MAX_RINGS_PER_PF_PASS_1_1;
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max_possible_vfs = CN23XX_MAX_VFS_PER_PF_PASS_1_1;
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break;
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default:
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total_rings = CN23XX_MAX_RINGS_PER_PF;
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max_rings = CN23XX_MAX_RINGS_PER_PF;
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max_possible_vfs = CN23XX_MAX_VFS_PER_PF;
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break;
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}
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if (!oct->sriov_info.num_pf_rings) {
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if (total_rings > num_present_cpus())
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num_pf_rings = num_present_cpus();
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else
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num_pf_rings = total_rings;
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} else {
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num_pf_rings = oct->sriov_info.num_pf_rings;
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if (num_pf_rings > total_rings) {
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dev_warn(&oct->pci_dev->dev,
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"num_queues_per_pf requested %u is more than available rings. Reducing to %u\n",
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num_pf_rings, total_rings);
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num_pf_rings = total_rings;
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}
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}
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if (max_rings <= num_present_cpus())
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num_pf_rings = 1;
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else
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num_pf_rings = num_present_cpus();
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#ifdef CONFIG_PCI_IOV
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max_vfs = min_t(u32,
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(max_rings - num_pf_rings), max_possible_vfs);
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rings_per_vf = 1;
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#else
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max_vfs = 0;
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rings_per_vf = 0;
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#endif
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total_rings = num_pf_rings + max_vfs;
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total_rings = num_pf_rings;
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/* the first ring of the pf */
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pf_srn = total_rings - num_pf_rings;
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oct->sriov_info.trs = total_rings;
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oct->sriov_info.max_vfs = max_vfs;
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oct->sriov_info.rings_per_vf = rings_per_vf;
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oct->sriov_info.pf_srn = pf_srn;
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oct->sriov_info.num_pf_rings = num_pf_rings;
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dev_dbg(&oct->pci_dev->dev, "trs:%d pf_srn:%d num_pf_rings:%d\n",
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oct->sriov_info.trs, oct->sriov_info.pf_srn,
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oct->sriov_info.num_pf_rings);
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dev_notice(&oct->pci_dev->dev, "trs:%d max_vfs:%d rings_per_vf:%d pf_srn:%d num_pf_rings:%d\n",
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oct->sriov_info.trs, oct->sriov_info.max_vfs,
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oct->sriov_info.rings_per_vf, oct->sriov_info.pf_srn,
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oct->sriov_info.num_pf_rings);
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oct->sriov_info.sriov_enabled = 0;
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return 0;
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}
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@ -65,9 +65,15 @@
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#define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2
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/* CN23xx IQ configuration macros */
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#define CN23XX_MAX_VFS_PER_PF_PASS_1_0 8
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#define CN23XX_MAX_VFS_PER_PF_PASS_1_1 31
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#define CN23XX_MAX_VFS_PER_PF 63
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#define CN23XX_MAX_RINGS_PER_VF 8
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#define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
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#define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
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#define CN23XX_MAX_RINGS_PER_PF 64
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#define CN23XX_MAX_RINGS_PER_VF 8
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#define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
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#define CN23XX_MAX_IQ_DESCRIPTORS 2048
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@ -322,11 +322,21 @@ struct octeon_pf_vf_hs_word {
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};
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struct octeon_sriov_info {
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/* Number of rings assigned to VF */
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u32 rings_per_vf;
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/** Max Number of VF devices that can be enabled. This variable can
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* specified during load time or it will be derived after allocating
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* PF queues. When max_vfs is derived then each VF will get one queue
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**/
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u32 max_vfs;
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/* Actual rings left for PF device */
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u32 num_pf_rings;
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/* SRN of PF usable IO queues */
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/* SRN of PF usable IO queues */
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u32 pf_srn;
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/* total pf rings */
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u32 trs;
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