Merge branch 'drm-fixes-4.18' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
A few fixes for 4.18: - fix a read past the end of an array due to vega20 changes - fix driver on systems with non-4K pages - fix locking with pageflipping in DC that could lead to a sleep while atomic - fix VCN firmware version reporting for upcoming firmware Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180628032641.2765-1-alexander.deucher@amd.com
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d12bce954e
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@ -376,7 +376,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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struct amdgpu_device *adev = ring->adev;
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uint64_t index;
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if (ring != &adev->uvd.inst[ring->me].ring) {
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if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
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ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
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ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
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} else {
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@ -52,7 +52,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
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unsigned long bo_size;
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const char *fw_name;
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const struct common_firmware_header *hdr;
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unsigned version_major, version_minor, family_id;
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unsigned char fw_check;
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int r;
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INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
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@ -83,12 +83,33 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
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hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
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adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
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family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
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version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
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version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
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DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
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version_major, version_minor, family_id);
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/* Bit 20-23, it is encode major and non-zero for new naming convention.
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* This field is part of version minor and DRM_DISABLED_FLAG in old naming
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* convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
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* is zero in old naming convention, this field is always zero so far.
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* These four bits are used to tell which naming convention is present.
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*/
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fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
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if (fw_check) {
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unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
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fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
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enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
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enc_major = fw_check;
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dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
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vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
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DRM_INFO("Found VCN firmware Version ENC: %hu.%hu DEC: %hu VEP: %hu Revision: %hu\n",
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enc_major, enc_minor, dec_ver, vep, fw_rev);
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} else {
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unsigned int version_major, version_minor, family_id;
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family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
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version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
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version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
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DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n",
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version_major, version_minor, family_id);
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}
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bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
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+ AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
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@ -1463,7 +1463,9 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
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uint64_t count;
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max_entries = min(max_entries, 16ull * 1024ull);
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for (count = 1; count < max_entries; ++count) {
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for (count = 1;
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count < max_entries / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
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++count) {
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uint64_t idx = pfn + count;
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if (pages_addr[idx] !=
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@ -1476,7 +1478,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
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dma_addr = pages_addr;
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} else {
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addr = pages_addr[pfn];
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max_entries = count;
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max_entries = count * (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
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}
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} else if (flags & AMDGPU_PTE_VALID) {
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@ -1491,7 +1493,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
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if (r)
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return r;
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pfn += last - start + 1;
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pfn += (last - start + 1) / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
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if (nodes && nodes->size == pfn) {
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pfn = 0;
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++nodes;
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@ -3928,10 +3928,11 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
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if (acrtc->base.state->event)
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prepare_flip_isr(acrtc);
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
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surface_updates->flip_addr = &addr;
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dc_commit_updates_for_stream(adev->dm.dc,
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surface_updates,
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1,
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@ -3944,9 +3945,6 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
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__func__,
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addr.address.grph.addr.high_part,
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addr.address.grph.addr.low_part);
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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}
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/*
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