drm/amd/pm: Removed fixed clock in auto mode DPM
SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM. Suggested-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -563,6 +563,8 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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struct smu10_hwmgr *data = hwmgr->backend;
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struct smu10_hwmgr *data = hwmgr->backend;
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uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
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uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
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uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
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uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
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uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
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uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
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if (hwmgr->smu_version < 0x1E3700) {
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if (hwmgr->smu_version < 0x1E3700) {
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pr_info("smu firmware version too old, can not set dpm level\n");
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pr_info("smu firmware version too old, can not set dpm level\n");
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@ -676,13 +678,13 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinFclkByFreq,
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PPSMC_MSG_SetHardMinFclkByFreq,
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hwmgr->display_config->num_display > 3 ?
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hwmgr->display_config->num_display > 3 ?
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SMU10_UMD_PSTATE_PEAK_FCLK :
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data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
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min_mclk,
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min_mclk,
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NULL);
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinSocclkByFreq,
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PPSMC_MSG_SetHardMinSocclkByFreq,
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SMU10_UMD_PSTATE_MIN_SOCCLK,
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data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
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NULL);
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinVcn,
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PPSMC_MSG_SetHardMinVcn,
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@ -695,11 +697,11 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
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NULL);
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxFclkByFreq,
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PPSMC_MSG_SetSoftMaxFclkByFreq,
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SMU10_UMD_PSTATE_PEAK_FCLK,
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data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
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NULL);
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxSocclkByFreq,
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PPSMC_MSG_SetSoftMaxSocclkByFreq,
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SMU10_UMD_PSTATE_PEAK_SOCCLK,
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data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
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NULL);
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NULL);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMaxVcn,
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PPSMC_MSG_SetSoftMaxVcn,
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