drm/nouveau: give a slightly larger pci(e)gart aperture on all chipsets
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
78c2018658
commit
d0f3c7e41d
|
@ -341,10 +341,10 @@ nouveau_sgdma_init(struct drm_device *dev)
|
||||||
u32 aper_size, align;
|
u32 aper_size, align;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
if (dev_priv->card_type >= NV_40 && pci_is_pcie(dev->pdev))
|
if (dev_priv->card_type >= NV_40)
|
||||||
aper_size = 512 * 1024 * 1024;
|
aper_size = 512 * 1024 * 1024;
|
||||||
else
|
else
|
||||||
aper_size = 64 * 1024 * 1024;
|
aper_size = 128 * 1024 * 1024;
|
||||||
|
|
||||||
/* Dear NVIDIA, NV44+ would like proper present bits in PTEs for
|
/* Dear NVIDIA, NV44+ would like proper present bits in PTEs for
|
||||||
* christmas. The cards before it have them, the cards after
|
* christmas. The cards before it have them, the cards after
|
||||||
|
|
|
@ -41,12 +41,8 @@ int nv04_instmem_init(struct drm_device *dev)
|
||||||
rsvd += 16 * 1024;
|
rsvd += 16 * 1024;
|
||||||
rsvd *= dev_priv->engine.fifo.channels;
|
rsvd *= dev_priv->engine.fifo.channels;
|
||||||
|
|
||||||
/* pciegart table */
|
rsvd += 512 * 1024; /* pci(e)gart table */
|
||||||
if (pci_is_pcie(dev->pdev))
|
rsvd += 512 * 1024; /* object storage */
|
||||||
rsvd += 512 * 1024;
|
|
||||||
|
|
||||||
/* object storage */
|
|
||||||
rsvd += 512 * 1024;
|
|
||||||
|
|
||||||
dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);
|
dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);
|
||||||
} else {
|
} else {
|
||||||
|
|
Loading…
Reference in New Issue