mtip32xx: recovery from command timeout
To recover from command timeouts, reset the device. In addition to that improved timeout handling of PIO commands. Signed-off-by: Sam Bradshaw <sbradshaw@micron.com> Signed-off-by: Asai Thambi S P <asamymuthupa@micron.com> Signed-off-by: Jens Axboe <axboe@kernel.dk>
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c678ef5286
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d0d096b1d8
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@ -243,40 +243,31 @@ static inline void release_slot(struct mtip_port *port, int tag)
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/*
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* Reset the HBA (without sleeping)
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*
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* Just like hba_reset, except does not call sleep, so can be
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* run from interrupt/tasklet context.
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*
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* @dd Pointer to the driver data structure.
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*
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* return value
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* 0 The reset was successful.
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* -1 The HBA Reset bit did not clear.
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*/
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static int hba_reset_nosleep(struct driver_data *dd)
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static int mtip_hba_reset(struct driver_data *dd)
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{
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unsigned long timeout;
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/* Chip quirk: quiesce any chip function */
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mdelay(10);
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/* Set the reset bit */
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writel(HOST_RESET, dd->mmio + HOST_CTL);
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/* Flush */
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readl(dd->mmio + HOST_CTL);
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/*
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* Wait 10ms then spin for up to 1 second
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* waiting for reset acknowledgement
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*/
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timeout = jiffies + msecs_to_jiffies(1000);
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mdelay(10);
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while ((readl(dd->mmio + HOST_CTL) & HOST_RESET)
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&& time_before(jiffies, timeout))
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mdelay(1);
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/* Spin for up to 2 seconds, waiting for reset acknowledgement */
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timeout = jiffies + msecs_to_jiffies(2000);
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do {
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mdelay(10);
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if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag))
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return -1;
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if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag))
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return -1;
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} while ((readl(dd->mmio + HOST_CTL) & HOST_RESET)
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&& time_before(jiffies, timeout));
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if (readl(dd->mmio + HOST_CTL) & HOST_RESET)
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return -1;
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@ -481,7 +472,7 @@ static void mtip_restart_port(struct mtip_port *port)
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dev_warn(&port->dd->pdev->dev,
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"PxCMD.CR not clear, escalating reset\n");
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if (hba_reset_nosleep(port->dd))
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if (mtip_hba_reset(port->dd))
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dev_err(&port->dd->pdev->dev,
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"HBA reset escalation failed.\n");
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@ -527,6 +518,26 @@ static void mtip_restart_port(struct mtip_port *port)
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}
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static int mtip_device_reset(struct driver_data *dd)
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{
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int rv = 0;
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if (mtip_check_surprise_removal(dd->pdev))
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return 0;
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if (mtip_hba_reset(dd) < 0)
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rv = -EFAULT;
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mdelay(1);
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mtip_init_port(dd->port);
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mtip_start_port(dd->port);
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/* Enable interrupts on the HBA. */
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writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,
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dd->mmio + HOST_CTL);
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return rv;
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}
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/*
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* Helper function for tag logging
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*/
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@ -632,7 +643,7 @@ static void mtip_timeout_function(unsigned long int data)
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if (cmdto_cnt) {
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print_tags(port->dd, "timed out", tagaccum, cmdto_cnt);
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if (!test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags)) {
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mtip_restart_port(port);
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mtip_device_reset(port->dd);
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wake_up_interruptible(&port->svc_wait);
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}
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clear_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags);
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@ -1283,11 +1294,11 @@ static int mtip_exec_internal_command(struct mtip_port *port,
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int rv = 0, ready2go = 1;
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struct mtip_cmd *int_cmd = &port->commands[MTIP_TAG_INTERNAL];
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unsigned long to;
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struct driver_data *dd = port->dd;
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/* Make sure the buffer is 8 byte aligned. This is asic specific. */
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if (buffer & 0x00000007) {
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dev_err(&port->dd->pdev->dev,
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"SG buffer is not 8 byte aligned\n");
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dev_err(&dd->pdev->dev, "SG buffer is not 8 byte aligned\n");
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return -EFAULT;
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}
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@ -1300,23 +1311,21 @@ static int mtip_exec_internal_command(struct mtip_port *port,
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mdelay(100);
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} while (time_before(jiffies, to));
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if (!ready2go) {
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dev_warn(&port->dd->pdev->dev,
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dev_warn(&dd->pdev->dev,
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"Internal cmd active. new cmd [%02X]\n", fis->command);
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return -EBUSY;
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}
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set_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
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port->ic_pause_timer = 0;
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if (fis->command == ATA_CMD_SEC_ERASE_UNIT)
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clear_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
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else if (fis->command == ATA_CMD_DOWNLOAD_MICRO)
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clear_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
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clear_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
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clear_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
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if (atomic == GFP_KERNEL) {
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if (fis->command != ATA_CMD_STANDBYNOW1) {
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/* wait for io to complete if non atomic */
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if (mtip_quiesce_io(port, 5000) < 0) {
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dev_warn(&port->dd->pdev->dev,
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dev_warn(&dd->pdev->dev,
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"Failed to quiesce IO\n");
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release_slot(port, MTIP_TAG_INTERNAL);
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clear_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
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@ -1361,58 +1370,84 @@ static int mtip_exec_internal_command(struct mtip_port *port,
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/* Issue the command to the hardware */
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mtip_issue_non_ncq_command(port, MTIP_TAG_INTERNAL);
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/* Poll if atomic, wait_for_completion otherwise */
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if (atomic == GFP_KERNEL) {
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/* Wait for the command to complete or timeout. */
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if (wait_for_completion_timeout(
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if (wait_for_completion_interruptible_timeout(
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&wait,
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msecs_to_jiffies(timeout)) == 0) {
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dev_err(&port->dd->pdev->dev,
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"Internal command did not complete [%d] "
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"within timeout of %lu ms\n",
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atomic, timeout);
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if (mtip_check_surprise_removal(port->dd->pdev) ||
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msecs_to_jiffies(timeout)) <= 0) {
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if (rv == -ERESTARTSYS) { /* interrupted */
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dev_err(&dd->pdev->dev,
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"Internal command [%02X] was interrupted after %lu ms\n",
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fis->command, timeout);
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rv = -EINTR;
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goto exec_ic_exit;
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} else if (rv == 0) /* timeout */
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dev_err(&dd->pdev->dev,
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"Internal command did not complete [%02X] within timeout of %lu ms\n",
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fis->command, timeout);
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else
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dev_err(&dd->pdev->dev,
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"Internal command [%02X] wait returned code [%d] after %lu ms - unhandled\n",
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fis->command, rv, timeout);
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if (mtip_check_surprise_removal(dd->pdev) ||
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test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
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&port->dd->dd_flag)) {
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&dd->dd_flag)) {
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dev_err(&dd->pdev->dev,
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"Internal command [%02X] wait returned due to SR\n",
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fis->command);
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rv = -ENXIO;
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goto exec_ic_exit;
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}
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mtip_device_reset(dd); /* recover from timeout issue */
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rv = -EAGAIN;
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goto exec_ic_exit;
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}
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} else {
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u32 hba_stat, port_stat;
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/* Spin for <timeout> checking if command still outstanding */
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timeout = jiffies + msecs_to_jiffies(timeout);
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while ((readl(port->cmd_issue[MTIP_TAG_INTERNAL])
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& (1 << MTIP_TAG_INTERNAL))
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&& time_before(jiffies, timeout)) {
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if (mtip_check_surprise_removal(port->dd->pdev)) {
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if (mtip_check_surprise_removal(dd->pdev)) {
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rv = -ENXIO;
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goto exec_ic_exit;
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}
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if ((fis->command != ATA_CMD_STANDBYNOW1) &&
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test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
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&port->dd->dd_flag)) {
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&dd->dd_flag)) {
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rv = -ENXIO;
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goto exec_ic_exit;
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}
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if (readl(port->mmio + PORT_IRQ_STAT) & PORT_IRQ_ERR) {
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atomic_inc(&int_cmd->active); /* error */
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break;
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port_stat = readl(port->mmio + PORT_IRQ_STAT);
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if (!port_stat)
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continue;
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if (port_stat & PORT_IRQ_ERR) {
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dev_err(&dd->pdev->dev,
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"Internal command [%02X] failed\n",
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fis->command);
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mtip_device_reset(dd);
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rv = -EIO;
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goto exec_ic_exit;
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} else {
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writel(port_stat, port->mmio + PORT_IRQ_STAT);
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hba_stat = readl(dd->mmio + HOST_IRQ_STAT);
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if (hba_stat)
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writel(hba_stat,
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dd->mmio + HOST_IRQ_STAT);
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}
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break;
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}
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}
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if (atomic_read(&int_cmd->active) > 1) {
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dev_err(&port->dd->pdev->dev,
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"Internal command [%02X] failed\n", fis->command);
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rv = -EIO;
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}
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if (readl(port->cmd_issue[MTIP_TAG_INTERNAL])
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& (1 << MTIP_TAG_INTERNAL)) {
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rv = -ENXIO;
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if (!test_bit(MTIP_DDF_REMOVE_PENDING_BIT,
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&port->dd->dd_flag)) {
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mtip_restart_port(port);
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if (!test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &dd->dd_flag)) {
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mtip_device_reset(dd);
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rv = -EAGAIN;
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}
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}
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@ -1724,7 +1759,8 @@ static int mtip_get_smart_attr(struct mtip_port *port, unsigned int id,
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* -EINVAL Invalid parameters passed in, trim not supported
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* -EIO Error submitting trim request to hw
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*/
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static int mtip_send_trim(struct driver_data *dd, unsigned int lba, unsigned int len)
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static int mtip_send_trim(struct driver_data *dd, unsigned int lba,
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unsigned int len)
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{
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int i, rv = 0;
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u64 tlba, tlen, sect_left;
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@ -1810,45 +1846,6 @@ static bool mtip_hw_get_capacity(struct driver_data *dd, sector_t *sectors)
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return (bool) !!port->identify_valid;
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}
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/*
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* Reset the HBA.
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*
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* Resets the HBA by setting the HBA Reset bit in the Global
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* HBA Control register. After setting the HBA Reset bit the
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* function waits for 1 second before reading the HBA Reset
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* bit to make sure it has cleared. If HBA Reset is not clear
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* an error is returned. Cannot be used in non-blockable
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* context.
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*
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* @dd Pointer to the driver data structure.
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*
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* return value
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* 0 The reset was successful.
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* -1 The HBA Reset bit did not clear.
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*/
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static int mtip_hba_reset(struct driver_data *dd)
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{
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mtip_deinit_port(dd->port);
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/* Set the reset bit */
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writel(HOST_RESET, dd->mmio + HOST_CTL);
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/* Flush */
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readl(dd->mmio + HOST_CTL);
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/* Wait for reset to clear */
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ssleep(1);
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/* Check the bit has cleared */
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if (readl(dd->mmio + HOST_CTL) & HOST_RESET) {
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dev_err(&dd->pdev->dev,
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"Reset bit did not clear.\n");
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return -1;
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}
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return 0;
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}
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/*
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* Display the identify command data.
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*
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