mmc: sdhci-esdhc-imx: Fix some English mistakes and typos
Fix various English mistakes and typos in comments and in printed strings. Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Benoît Thébaudeau
Ulf Hansson
parent
16f2e0c6ff
commit
d04f8d5b94
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@ -95,7 +95,7 @@
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#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
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/*
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* There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
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* There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
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* Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
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* but bit28 is used as the INT DMA ERR in fsl eSDHC design.
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* Define this macro DMA error INT for fsl eSDHC
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@ -110,12 +110,12 @@
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* In exact block transfer, the controller doesn't complete the
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* operations automatically as required at the end of the
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* transfer and remains on hold if the abort command is not sent.
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* As a result, the TC flag is not asserted and SW received timeout
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* exeception. Bit1 of Vendor Spec registor is used to fix it.
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* As a result, the TC flag is not asserted and SW received timeout
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* exception. Bit1 of Vendor Spec register is used to fix it.
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*/
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#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
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/*
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* The flag enables the workaround for ESDHC errata ENGcm07207 which
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* The flag enables the workaround for ESDHC erratum ENGcm07207 which
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* affects i.MX25 and i.MX35.
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*/
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#define ESDHC_FLAG_ENGCM07207 BIT(2)
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@ -131,7 +131,7 @@
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/* The IP has SDHCI_CAPABILITIES_1 register */
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#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
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/*
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* The IP has errata ERR004536
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* The IP has erratum ERR004536
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* uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
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* when reading data from the card
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*/
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@ -141,7 +141,7 @@
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/* The IP supports HS400 mode */
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#define ESDHC_FLAG_HS400 BIT(9)
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/* A higher clock ferquency than this rate requires strobell dll control */
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/* A clock frequency higher than this rate requires strobe dll control */
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#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
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struct esdhc_soc_data {
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@ -197,7 +197,7 @@ struct pltfm_imx_data {
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struct clk *clk_ahb;
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struct clk *clk_per;
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enum {
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NO_CMD_PENDING, /* no multiblock command pending*/
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NO_CMD_PENDING, /* no multiblock command pending */
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MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
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WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
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} multiblock_status;
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@ -286,7 +286,7 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
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* ADMA2 capability of esdhc, but this bit is messed up on
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* some SOCs (e.g. on MX25, MX35 this bit is set, but they
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* don't actually support ADMA2). So set the BROKEN_ADMA
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* uirk on MX25/35 platforms.
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* quirk on MX25/35 platforms.
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*/
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if (val & SDHCI_CAN_DO_ADMA1) {
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@ -351,7 +351,7 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
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if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
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/*
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* Clear and then set D3CD bit to avoid missing the
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* card interrupt. This is a eSDHC controller problem
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* card interrupt. This is an eSDHC controller problem
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* so we need to apply the following workaround: clear
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* and set D3CD bit will make eSDHC re-sample the card
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* interrupt. In case a card interrupt was lost,
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@ -604,7 +604,7 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
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* Do not touch buswidth bits here. This is done in
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* esdhc_pltfm_bus_width.
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* Do not touch the D3CD bit either which is used for the
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* SDIO interrupt errata workaround.
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* SDIO interrupt erratum workaround.
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*/
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mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
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@ -763,7 +763,7 @@ static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
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writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
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writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
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dev_dbg(mmc_dev(host->mmc),
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"tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
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"tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
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val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
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}
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@ -807,7 +807,7 @@ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
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ret = mmc_send_tuning(host->mmc, opcode, NULL);
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esdhc_post_tuning(host);
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dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
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dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
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ret ? "failed" : "passed", avg, ret);
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return ret;
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@ -847,15 +847,15 @@ static int esdhc_change_pinstate(struct sdhci_host *host,
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}
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/*
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* For HS400 eMMC, there is a data_strobe line, this signal is generated
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* For HS400 eMMC, there is a data_strobe line. This signal is generated
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* by the device and used for data output and CRC status response output
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* in HS400 mode. The frequency of this signal follows the frequency of
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* CLK generated by host. Host receive the data which is aligned to the
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* CLK generated by host. The host receives the data which is aligned to the
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* edge of data_strobe line. Due to the time delay between CLK line and
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* data_strobe line, if the delay time is larger than one clock cycle,
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* then CLK and data_strobe line will misaligned, read error shows up.
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* then CLK and data_strobe line will be misaligned, read error shows up.
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* So when the CLK is higher than 100MHz, each clock cycle is short enough,
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* host should config the delay target.
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* host should configure the delay target.
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*/
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static void esdhc_set_strobe_dll(struct sdhci_host *host)
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{
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@ -895,7 +895,7 @@ static void esdhc_reset_tuning(struct sdhci_host *host)
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struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
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u32 ctrl;
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/* Rest the tuning circurt */
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/* Reset the tuning circuit */
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if (esdhc_is_usdhc(imx_data)) {
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if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
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ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
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@ -976,7 +976,7 @@ static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
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/* Doc Errata: the uSDHC actual maximum timeout count is 1 << 29 */
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/* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
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return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
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}
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@ -1032,10 +1032,10 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
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/*
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* ROM code will change the bit burst_length_enable setting
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* to zero if this usdhc is choosed to boot system. Change
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* to zero if this usdhc is chosen to boot system. Change
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* it back here, otherwise it will impact the performance a
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* lot. This bit is used to enable/disable the burst length
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* for the external AHB2AXI bridge, it's usefully especially
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* for the external AHB2AXI bridge. It's useful especially
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* for INCR transfer because without burst length indicator,
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* the AHB2AXI bridge does not know the burst length in
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* advance. And without burst length indicator, AHB INCR
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@ -1045,7 +1045,7 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
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| ESDHC_BURST_LEN_EN_INCR,
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host->ioaddr + SDHCI_HOST_CONTROL);
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/*
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* errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
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* erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
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* TO1.1, it's harmless for MX6SL
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*/
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writel(readl(host->ioaddr + 0x6c) | BIT(7),
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@ -1104,7 +1104,7 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
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mmc_of_parse_voltage(np, &host->ocr_mask);
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/* sdr50 and sdr104 needs work on 1.8v signal voltage */
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/* sdr50 and sdr104 need work on 1.8v signal voltage */
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if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
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!IS_ERR(imx_data->pins_default)) {
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imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
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@ -1116,7 +1116,8 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
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dev_warn(mmc_dev(host->mmc),
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"could not get ultra high speed state, work on normal mode\n");
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/*
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* fall back to not support uhs by specify no 1.8v quirk
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* fall back to not supporting uhs by specifying no
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* 1.8v quirk
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*/
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host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
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}
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@ -1272,7 +1273,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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dev_warn(mmc_dev(host->mmc), "could not get default state\n");
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if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
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/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
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/* Fix erratum ENGcm07207 present on i.MX25 and i.MX35 */
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host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
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| SDHCI_QUIRK_BROKEN_ADMA;
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