ARM: 6450/1: Fix checkpatch.pl issues in arch/arm/mach-sa1100/cpu-sa1100.c.
This patch fixes checkpatch.pl issues in arch/arm/mach-sa1100/cpu-sa1100.c. Signed-off-by: Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -94,48 +94,47 @@
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#include "generic.h"
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typedef struct {
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struct sa1100_dram_regs {
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int speed;
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u32 mdcnfg;
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u32 mdcas0;
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u32 mdcas1;
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u32 mdcas2;
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} sa1100_dram_regs_t;
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};
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static struct cpufreq_driver sa1100_driver;
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static sa1100_dram_regs_t sa1100_dram_settings[] =
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{
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/* speed, mdcnfg, mdcas0, mdcas1, mdcas2 clock frequency */
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{ 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 59.0 MHz */
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{ 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 73.7 MHz */
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{ 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 88.5 MHz */
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{ 103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 103.2 MHz */
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{ 118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 118.0 MHz */
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{ 132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 132.7 MHz */
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{ 147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff }, /* 147.5 MHz */
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{ 162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff }, /* 162.2 MHz */
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{ 176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff }, /* 176.9 MHz */
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{ 191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff }, /* 191.7 MHz */
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{ 206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 206.4 MHz */
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{ 221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 221.2 MHz */
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{ 235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1 }, /* 235.9 MHz */
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{ 250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 250.7 MHz */
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{ 265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 265.4 MHz */
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{ 280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87 }, /* 280.2 MHz */
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static struct sa1100_dram_regs sa1100_dram_settings[] = {
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/*speed, mdcnfg, mdcas0, mdcas1, mdcas2, clock freq */
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{ 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 59.0 MHz */
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{ 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 73.7 MHz */
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{ 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 88.5 MHz */
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{103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
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{118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
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{132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
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{147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
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{162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
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{176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
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{191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
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{206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
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{221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
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{235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
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{250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
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{265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
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{280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
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{ 0, 0, 0, 0, 0 } /* last entry */
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};
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static void sa1100_update_dram_timings(int current_speed, int new_speed)
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{
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sa1100_dram_regs_t *settings = sa1100_dram_settings;
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struct sa1100_dram_regs *settings = sa1100_dram_settings;
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/* find speed */
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while (settings->speed != 0) {
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if(new_speed == settings->speed)
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if (new_speed == settings->speed)
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break;
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settings++;
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}
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@ -149,7 +148,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed)
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/* We're going FASTER, so first relax the memory
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* timings before changing the core frequency
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*/
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/* Half the memory access clock */
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MDCNFG |= MDCNFG_CDB2;
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@ -187,7 +186,7 @@ static int sa1100_target(struct cpufreq_policy *policy,
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struct cpufreq_freqs freqs;
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new_ppcr = sa11x0_freq_to_ppcr(target_freq);
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switch(relation){
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switch (relation) {
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case CPUFREQ_RELATION_L:
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if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
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new_ppcr--;
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