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x86: msr-index.h: define EPB mid-points 

These are currently open-coded into intel_pstate.c

Signed-off-by: Len Brown <len.brown@intel.com>
This commit is contained in:
Len Brown 2017-02-25 18:18:22 -05:00
parent c470abd4fd
commit d0117a0e27
1 changed files with 5 additions and 3 deletions
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8
arch/x86/include/asm/msr-index.h
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@ -462,9 +462,11 @@
#define MSR_MISC_PWR_MGMT 0x000001aa
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
#define ENERGY_PERF_BIAS_PERFORMANCE 0
#define ENERGY_PERF_BIAS_NORMAL 6
#define ENERGY_PERF_BIAS_POWERSAVE 15
#define ENERGY_PERF_BIAS_PERFORMANCE 0
#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
#define ENERGY_PERF_BIAS_NORMAL 6
#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1