clk: sunxi: factors: Consolidate get_factors parameters into a struct
The .get_factors callback of factors_clk has 6 parameters. To extend factors_clk in any way that requires adding parameters to .get_factors would make that list even longer, not to mention changing all the function declarations. Do this once now and consolidate all the parameters into a struct. Also drop the space before function pointer arguments, since checkpatch complains. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai
Maxime Ripard
parent
4cbeaebb8a
commit
cfa6368860
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@ -73,8 +73,13 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct clk_factors *factors = to_clk_factors(hw);
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factors->get_factors((u32 *)&rate, (u32)*parent_rate,
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NULL, NULL, NULL, NULL);
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struct factors_request req = {
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.rate = rate,
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.parent_rate = *parent_rate,
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};
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factors->get_factors(&req);
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return rate;
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}
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@ -120,13 +125,16 @@ static int clk_factors_determine_rate(struct clk_hw *hw,
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static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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u8 n = 0, k = 0, m = 0, p = 0;
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struct factors_request req = {
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.rate = rate,
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.parent_rate = parent_rate,
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};
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u32 reg;
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struct clk_factors *factors = to_clk_factors(hw);
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const struct clk_factors_config *config = factors->config;
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unsigned long flags = 0;
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factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p);
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factors->get_factors(&req);
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if (factors->lock)
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spin_lock_irqsave(factors->lock, flags);
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@ -135,10 +143,10 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
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reg = readl(factors->reg);
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/* Set up the new factors - macros do not do anything if width is 0 */
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reg = FACTOR_SET(config->nshift, config->nwidth, reg, n);
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reg = FACTOR_SET(config->kshift, config->kwidth, reg, k);
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reg = FACTOR_SET(config->mshift, config->mwidth, reg, m);
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reg = FACTOR_SET(config->pshift, config->pwidth, reg, p);
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reg = FACTOR_SET(config->nshift, config->nwidth, reg, req.n);
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reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k);
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reg = FACTOR_SET(config->mshift, config->mwidth, reg, req.m);
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reg = FACTOR_SET(config->pshift, config->pwidth, reg, req.p);
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/* Apply them now */
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writel(reg, factors->reg);
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@ -19,12 +19,21 @@ struct clk_factors_config {
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u8 n_start;
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};
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struct factors_request {
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unsigned long rate;
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unsigned long parent_rate;
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u8 n;
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u8 k;
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u8 m;
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u8 p;
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};
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struct factors_data {
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int enable;
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int mux;
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int muxmask;
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const struct clk_factors_config *table;
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
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void (*getter)(struct factors_request *req);
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const char *name;
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};
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@ -32,7 +41,7 @@ struct clk_factors {
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struct clk_hw hw;
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void __iomem *reg;
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const struct clk_factors_config *config;
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void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
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void (*get_factors)(struct factors_request *req);
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spinlock_t *lock;
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/* for cleanup */
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struct clk_mux *mux;
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@ -28,17 +28,16 @@
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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static void sun4i_a10_get_mod0_factors(struct factors_request *req)
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{
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u8 div, calcm, calcp;
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/* These clocks can only divide, so we will never be able to achieve
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* frequencies higher than the parent frequency */
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if (*freq > parent_rate)
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*freq = parent_rate;
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if (req->rate > req->parent_rate)
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req->rate = req->parent_rate;
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div = DIV_ROUND_UP(parent_rate, *freq);
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div = DIV_ROUND_UP(req->parent_rate, req->rate);
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if (div < 16)
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calcp = 0;
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@ -51,14 +50,9 @@ static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
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calcm = DIV_ROUND_UP(div, 1 << calcp);
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*freq = (parent_rate >> calcp) / calcm;
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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*m = calcm - 1;
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*p = calcp;
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req->rate = (req->parent_rate >> calcp) / calcm;
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req->m = calcm - 1;
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req->p = calcp;
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}
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/* user manual says "n" but it's really "p" */
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@ -26,8 +26,7 @@
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* rate = parent_rate / (m + 1);
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*/
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static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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static void sun8i_a23_get_mbus_factors(struct factors_request *req)
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{
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u8 div;
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@ -35,21 +34,16 @@ static void sun8i_a23_get_mbus_factors(u32 *freq, u32 parent_rate,
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* These clocks can only divide, so we will never be able to
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* achieve frequencies higher than the parent frequency
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*/
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if (*freq > parent_rate)
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*freq = parent_rate;
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if (req->rate > req->parent_rate)
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req->rate = req->parent_rate;
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div = DIV_ROUND_UP(parent_rate, *freq);
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div = DIV_ROUND_UP(req->parent_rate, req->rate);
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if (div > 8)
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div = 8;
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*freq = parent_rate / div;
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/* we were called to round the frequency, we can now return */
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if (m == NULL)
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return;
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*m = div - 1;
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req->rate = req->parent_rate / div;
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req->m = div - 1;
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}
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static struct clk_factors_config sun8i_a23_mbus_config = {
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@ -32,15 +32,14 @@
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* p and m are named div1 and div2 in Allwinner's SDK
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*/
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static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate,
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u8 *n_ret, u8 *k, u8 *m_ret, u8 *p_ret)
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static void sun9i_a80_get_pll4_factors(struct factors_request *req)
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{
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int n;
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int m = 1;
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int p = 1;
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/* Normalize value to a 6 MHz multiple (24 MHz / 4) */
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n = DIV_ROUND_UP(*freq, 6000000);
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n = DIV_ROUND_UP(req->rate, 6000000);
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/* If n is too large switch to steps of 12 MHz */
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if (n > 255) {
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@ -60,15 +59,10 @@ static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate,
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else if (n < 12)
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n = 12;
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*freq = ((24000000 * n) >> p) / (m + 1);
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/* we were called to round the frequency, we can now return */
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if (n_ret == NULL)
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return;
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*n_ret = n;
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*m_ret = m;
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*p_ret = p;
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req->rate = ((24000000 * n) >> p) / (m + 1);
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req->n = n;
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req->m = m;
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req->p = p;
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}
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static const struct clk_factors_config sun9i_a80_pll4_config = {
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@ -111,27 +105,21 @@ CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_se
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* rate = parent_rate / (m + 1);
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*/
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static void sun9i_a80_get_gt_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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static void sun9i_a80_get_gt_factors(struct factors_request *req)
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{
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u32 div;
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if (parent_rate < *freq)
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*freq = parent_rate;
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if (req->parent_rate < req->rate)
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req->rate = req->parent_rate;
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div = DIV_ROUND_UP(parent_rate, *freq);
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div = DIV_ROUND_UP(req->parent_rate, req->rate);
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/* maximum divider is 4 */
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if (div > 4)
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div = 4;
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*freq = parent_rate / div;
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/* we were called to round the frequency, we can now return */
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if (!m)
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return;
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*m = div;
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req->rate = req->parent_rate / div;
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req->m = div;
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}
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static const struct clk_factors_config sun9i_a80_gt_config = {
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@ -176,27 +164,21 @@ CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
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* rate = parent_rate >> p;
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*/
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static void sun9i_a80_get_ahb_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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static void sun9i_a80_get_ahb_factors(struct factors_request *req)
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{
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u32 _p;
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if (parent_rate < *freq)
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*freq = parent_rate;
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if (req->parent_rate < req->rate)
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req->rate = req->parent_rate;
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_p = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
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_p = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
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/* maximum p is 3 */
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if (_p > 3)
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_p = 3;
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*freq = parent_rate >> _p;
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/* we were called to round the frequency, we can now return */
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if (!p)
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return;
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*p = _p;
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req->rate = req->parent_rate >> _p;
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req->p = _p;
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}
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static const struct clk_factors_config sun9i_a80_ahb_config = {
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@ -262,31 +244,22 @@ CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_se
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sun9i_a80_get_apb1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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static void sun9i_a80_get_apb1_factors(struct factors_request *req)
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{
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u32 div;
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u8 calcm, calcp;
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if (parent_rate < *freq)
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*freq = parent_rate;
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if (req->parent_rate < req->rate)
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req->rate = req->parent_rate;
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div = DIV_ROUND_UP(parent_rate, *freq);
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div = DIV_ROUND_UP(req->parent_rate, req->rate);
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/* Highest possible divider is 256 (p = 3, m = 31) */
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if (div > 256)
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div = 256;
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calcp = order_base_2(div);
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calcm = (parent_rate >> calcp) - 1;
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*freq = (parent_rate >> calcp) / (calcm + 1);
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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*m = calcm;
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*p = calcp;
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req->p = order_base_2(div);
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req->m = (req->parent_rate >> req->p) - 1;
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req->rate = (req->parent_rate >> req->p) / (req->m + 1);
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}
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static const struct clk_factors_config sun9i_a80_apb1_config = {
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@ -246,49 +246,45 @@ CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_se
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* parent_rate is always 24Mhz
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*/
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static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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static void sun4i_get_pll1_factors(struct factors_request *req)
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{
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u8 div;
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/* Normalize value to a 6M multiple */
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div = *freq / 6000000;
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*freq = 6000000 * div;
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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div = req->rate / 6000000;
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req->rate = 6000000 * div;
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/* m is always zero for pll1 */
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*m = 0;
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req->m = 0;
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/* k is 1 only on these cases */
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if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
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*k = 1;
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if (req->rate >= 768000000 || req->rate == 42000000 ||
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req->rate == 54000000)
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req->k = 1;
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else
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*k = 0;
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req->k = 0;
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/* p will be 3 for divs under 10 */
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if (div < 10)
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*p = 3;
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req->p = 3;
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/* p will be 2 for divs between 10 - 20 and odd divs under 32 */
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else if (div < 20 || (div < 32 && (div & 1)))
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*p = 2;
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req->p = 2;
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/* p will be 1 for even divs under 32, divs under 40 and odd pairs
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* of divs between 40-62 */
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else if (div < 40 || (div < 64 && (div & 2)))
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*p = 1;
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req->p = 1;
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/* any other entries have p = 0 */
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else
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*p = 0;
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req->p = 0;
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/* calculate a suitable n based on k and p */
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div <<= *p;
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div /= (*k + 1);
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*n = div / 4;
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div <<= req->p;
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div /= (req->k + 1);
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req->n = div / 4;
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}
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/**
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@ -297,15 +293,14 @@ static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
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* rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
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* parent_rate should always be 24MHz
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*/
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static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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static void sun6i_a31_get_pll1_factors(struct factors_request *req)
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{
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/*
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* We can operate only on MHz, this will make our life easier
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* later.
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*/
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u32 freq_mhz = *freq / 1000000;
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u32 parent_freq_mhz = parent_rate / 1000000;
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u32 freq_mhz = req->rate / 1000000;
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u32 parent_freq_mhz = req->parent_rate / 1000000;
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/*
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* Round down the frequency to the closest multiple of either
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@ -319,28 +314,20 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
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else
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freq_mhz = round_freq_16;
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*freq = freq_mhz * 1000000;
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/*
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* If the factors pointer are null, we were just called to
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* round down the frequency.
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* Exit.
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*/
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if (n == NULL)
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return;
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req->rate = freq_mhz * 1000000;
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/* If the frequency is a multiple of 32 MHz, k is always 3 */
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if (!(freq_mhz % 32))
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*k = 3;
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req->k = 3;
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/* If the frequency is a multiple of 9 MHz, k is always 2 */
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else if (!(freq_mhz % 9))
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*k = 2;
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req->k = 2;
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/* If the frequency is a multiple of 8 MHz, k is always 1 */
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else if (!(freq_mhz % 8))
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*k = 1;
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req->k = 1;
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/* Otherwise, we don't use the k factor */
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else
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*k = 0;
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req->k = 0;
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/*
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* If the frequency is a multiple of 2 but not a multiple of
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@ -351,27 +338,28 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
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* somehow relates to this frequency.
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*/
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if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
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*m = 2;
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req->m = 2;
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/*
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* If the frequency is a multiple of 6MHz, but the factor is
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* odd, m will be 3
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*/
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else if ((freq_mhz / 6) & 1)
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*m = 3;
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req->m = 3;
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/* Otherwise, we end up with m = 1 */
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else
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*m = 1;
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req->m = 1;
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||||
|
||||
/* Calculate n thanks to the above factors we already got */
|
||||
*n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
|
||||
req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz)
|
||||
- 1;
|
||||
|
||||
/*
|
||||
* If n end up being outbound, and that we can still decrease
|
||||
* m, do it.
|
||||
*/
|
||||
if ((*n + 1) > 31 && (*m + 1) > 1) {
|
||||
*n = (*n + 1) / 2 - 1;
|
||||
*m = (*m + 1) / 2 - 1;
|
||||
if ((req->n + 1) > 31 && (req->m + 1) > 1) {
|
||||
req->n = (req->n + 1) / 2 - 1;
|
||||
req->m = (req->m + 1) / 2 - 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -382,45 +370,41 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
|
|||
* parent_rate is always 24Mhz
|
||||
*/
|
||||
|
||||
static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
static void sun8i_a23_get_pll1_factors(struct factors_request *req)
|
||||
{
|
||||
u8 div;
|
||||
|
||||
/* Normalize value to a 6M multiple */
|
||||
div = *freq / 6000000;
|
||||
*freq = 6000000 * div;
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (n == NULL)
|
||||
return;
|
||||
div = req->rate / 6000000;
|
||||
req->rate = 6000000 * div;
|
||||
|
||||
/* m is always zero for pll1 */
|
||||
*m = 0;
|
||||
req->m = 0;
|
||||
|
||||
/* k is 1 only on these cases */
|
||||
if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
|
||||
*k = 1;
|
||||
if (req->rate >= 768000000 || req->rate == 42000000 ||
|
||||
req->rate == 54000000)
|
||||
req->k = 1;
|
||||
else
|
||||
*k = 0;
|
||||
req->k = 0;
|
||||
|
||||
/* p will be 2 for divs under 20 and odd divs under 32 */
|
||||
if (div < 20 || (div < 32 && (div & 1)))
|
||||
*p = 2;
|
||||
req->p = 2;
|
||||
|
||||
/* p will be 1 for even divs under 32, divs under 40 and odd pairs
|
||||
* of divs between 40-62 */
|
||||
else if (div < 40 || (div < 64 && (div & 2)))
|
||||
*p = 1;
|
||||
req->p = 1;
|
||||
|
||||
/* any other entries have p = 0 */
|
||||
else
|
||||
*p = 0;
|
||||
req->p = 0;
|
||||
|
||||
/* calculate a suitable n based on k and p */
|
||||
div <<= *p;
|
||||
div /= (*k + 1);
|
||||
*n = div / 4 - 1;
|
||||
div <<= req->p;
|
||||
div /= (req->k + 1);
|
||||
req->n = div / 4 - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -430,29 +414,24 @@ static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
|
|||
* parent_rate is always 24Mhz
|
||||
*/
|
||||
|
||||
static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
static void sun4i_get_pll5_factors(struct factors_request *req)
|
||||
{
|
||||
u8 div;
|
||||
|
||||
/* Normalize value to a parent_rate multiple (24M) */
|
||||
div = *freq / parent_rate;
|
||||
*freq = parent_rate * div;
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (n == NULL)
|
||||
return;
|
||||
div = req->rate / req->parent_rate;
|
||||
req->rate = req->parent_rate * div;
|
||||
|
||||
if (div < 31)
|
||||
*k = 0;
|
||||
req->k = 0;
|
||||
else if (div / 2 < 31)
|
||||
*k = 1;
|
||||
req->k = 1;
|
||||
else if (div / 3 < 31)
|
||||
*k = 2;
|
||||
req->k = 2;
|
||||
else
|
||||
*k = 3;
|
||||
req->k = 3;
|
||||
|
||||
*n = DIV_ROUND_UP(div, (*k+1));
|
||||
req->n = DIV_ROUND_UP(div, (req->k + 1));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -462,24 +441,19 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
|
|||
* parent_rate is always 24Mhz
|
||||
*/
|
||||
|
||||
static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
static void sun6i_a31_get_pll6_factors(struct factors_request *req)
|
||||
{
|
||||
u8 div;
|
||||
|
||||
/* Normalize value to a parent_rate multiple (24M) */
|
||||
div = *freq / parent_rate;
|
||||
*freq = parent_rate * div;
|
||||
div = req->rate / req->parent_rate;
|
||||
req->rate = req->parent_rate * div;
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (n == NULL)
|
||||
return;
|
||||
req->k = div / 32;
|
||||
if (req->k > 3)
|
||||
req->k = 3;
|
||||
|
||||
*k = div / 32;
|
||||
if (*k > 3)
|
||||
*k = 3;
|
||||
|
||||
*n = DIV_ROUND_UP(div, (*k+1)) - 1;
|
||||
req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -488,37 +462,32 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
|
|||
* rate = parent_rate >> p
|
||||
*/
|
||||
|
||||
static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
static void sun5i_a13_get_ahb_factors(struct factors_request *req)
|
||||
{
|
||||
u32 div;
|
||||
|
||||
/* divide only */
|
||||
if (parent_rate < *freq)
|
||||
*freq = parent_rate;
|
||||
if (req->parent_rate < req->rate)
|
||||
req->rate = req->parent_rate;
|
||||
|
||||
/*
|
||||
* user manual says valid speed is 8k ~ 276M, but tests show it
|
||||
* can work at speeds up to 300M, just after reparenting to pll6
|
||||
*/
|
||||
if (*freq < 8000)
|
||||
*freq = 8000;
|
||||
if (*freq > 300000000)
|
||||
*freq = 300000000;
|
||||
if (req->rate < 8000)
|
||||
req->rate = 8000;
|
||||
if (req->rate > 300000000)
|
||||
req->rate = 300000000;
|
||||
|
||||
div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
|
||||
div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate));
|
||||
|
||||
/* p = 0 ~ 3 */
|
||||
if (div > 3)
|
||||
div = 3;
|
||||
|
||||
*freq = parent_rate >> div;
|
||||
req->rate = req->parent_rate >> div;
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (p == NULL)
|
||||
return;
|
||||
|
||||
*p = div;
|
||||
req->p = div;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -527,39 +496,34 @@ static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
|
|||
* rate = (parent_rate >> p) / (m + 1);
|
||||
*/
|
||||
|
||||
static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
static void sun4i_get_apb1_factors(struct factors_request *req)
|
||||
{
|
||||
u8 calcm, calcp;
|
||||
int div;
|
||||
|
||||
if (parent_rate < *freq)
|
||||
*freq = parent_rate;
|
||||
if (req->parent_rate < req->rate)
|
||||
req->rate = req->parent_rate;
|
||||
|
||||
parent_rate = DIV_ROUND_UP(parent_rate, *freq);
|
||||
div = DIV_ROUND_UP(req->parent_rate, req->rate);
|
||||
|
||||
/* Invalid rate! */
|
||||
if (parent_rate > 32)
|
||||
if (div > 32)
|
||||
return;
|
||||
|
||||
if (parent_rate <= 4)
|
||||
if (div <= 4)
|
||||
calcp = 0;
|
||||
else if (parent_rate <= 8)
|
||||
else if (div <= 8)
|
||||
calcp = 1;
|
||||
else if (parent_rate <= 16)
|
||||
else if (div <= 16)
|
||||
calcp = 2;
|
||||
else
|
||||
calcp = 3;
|
||||
|
||||
calcm = (parent_rate >> calcp) - 1;
|
||||
calcm = (req->parent_rate >> calcp) - 1;
|
||||
|
||||
*freq = (parent_rate >> calcp) / (calcm + 1);
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (n == NULL)
|
||||
return;
|
||||
|
||||
*m = calcm;
|
||||
*p = calcp;
|
||||
req->rate = (req->parent_rate >> calcp) / (calcm + 1);
|
||||
req->m = calcm;
|
||||
req->p = calcp;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -571,17 +535,16 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
|
|||
* rate = (parent_rate >> p) / (m + 1);
|
||||
*/
|
||||
|
||||
static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
|
||||
u8 *n, u8 *k, u8 *m, u8 *p)
|
||||
static void sun7i_a20_get_out_factors(struct factors_request *req)
|
||||
{
|
||||
u8 div, calcm, calcp;
|
||||
|
||||
/* These clocks can only divide, so we will never be able to achieve
|
||||
* frequencies higher than the parent frequency */
|
||||
if (*freq > parent_rate)
|
||||
*freq = parent_rate;
|
||||
if (req->rate > req->parent_rate)
|
||||
req->rate = req->parent_rate;
|
||||
|
||||
div = DIV_ROUND_UP(parent_rate, *freq);
|
||||
div = DIV_ROUND_UP(req->parent_rate, req->rate);
|
||||
|
||||
if (div < 32)
|
||||
calcp = 0;
|
||||
|
|
@ -594,14 +557,9 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
|
|||
|
||||
calcm = DIV_ROUND_UP(div, 1 << calcp);
|
||||
|
||||
*freq = (parent_rate >> calcp) / calcm;
|
||||
|
||||
/* we were called to round the frequency, we can now return */
|
||||
if (n == NULL)
|
||||
return;
|
||||
|
||||
*m = calcm - 1;
|
||||
*p = calcp;
|
||||
req->rate = (req->parent_rate >> calcp) / calcm;
|
||||
req->m = calcm - 1;
|
||||
req->p = calcp;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue