ASoC: SOF: topology: show clks_control value in dynamic debug
We log most of the SSP configurations except the clks_control. This will be used to enable bclk/mclk early start so it's useful to show the information to the user. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Bard Liao <bard.liao@intel.com> Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Link: https://lore.kernel.org/r/20211004212729.199550-2-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -2825,12 +2825,12 @@ static int sof_link_ssp_load(struct snd_soc_component *scomp, int index,
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config[i].ssp.rx_slots = le32_to_cpu(hw_config[i].rx_slots);
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config[i].ssp.tx_slots = le32_to_cpu(hw_config[i].tx_slots);
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dev_dbg(scomp->dev, "tplg: config SSP%d fmt 0x%x mclk %d bclk %d fclk %d width (%d)%d slots %d mclk id %d quirks %d\n",
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dev_dbg(scomp->dev, "tplg: config SSP%d fmt %#x mclk %d bclk %d fclk %d width (%d)%d slots %d mclk id %d quirks %d clks_control %#x\n",
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config[i].dai_index, config[i].format,
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config[i].ssp.mclk_rate, config[i].ssp.bclk_rate,
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config[i].ssp.fsync_rate, config[i].ssp.sample_valid_bits,
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config[i].ssp.tdm_slot_width, config[i].ssp.tdm_slots,
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config[i].ssp.mclk_id, config[i].ssp.quirks);
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config[i].ssp.mclk_id, config[i].ssp.quirks, config[i].ssp.clks_control);
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/* validate SSP fsync rate and channel count */
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if (config[i].ssp.fsync_rate < 8000 || config[i].ssp.fsync_rate > 192000) {
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