scsi: qla2xxx: Add SLER and PI control support
BIT_13 of extended FW attribute informs about NVMe-2 support. Set BIT_15 of special feature control block for enabling SLER in FW. Set bit 8 (SLER supported) to 1 for the service parameter information when sending NVMe PRLI request. Set BIT_14 of special feature control block for enabling PI Control in FW. Driver should set bit 9 (PI Control supported) to 1 for the service parameter information when sending NVMe PRLI request. Set BIT_13 for NVMe Async events. Link: https://lore.kernel.org/r/20200904045128.23631-13-njavali@marvell.com Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com> Signed-off-by: Saurav Kashyap <skashyap@marvell.com> Signed-off-by: Nilesh Javali <njavali@marvell.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -16,7 +16,7 @@
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* | Device Discovery | 0x2134 | 0x210e-0x2116 |
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* | | | 0x211a |
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* | | | 0x211c-0x2128 |
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* | | | 0x212a-0x2134 |
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* | | | 0x212c-0x2134 |
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* | Queue Command and IO tracing | 0x3074 | 0x300b |
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* | | | 0x3027-0x3028 |
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* | | | 0x303d-0x3041 |
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@ -2476,6 +2476,8 @@ typedef struct fc_port {
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struct completion nvme_del_done;
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uint32_t nvme_prli_service_param;
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#define NVME_PRLI_SP_PI_CTRL BIT_9
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#define NVME_PRLI_SP_SLER BIT_8
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#define NVME_PRLI_SP_CONF BIT_7
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#define NVME_PRLI_SP_INITIATOR BIT_5
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#define NVME_PRLI_SP_TARGET BIT_4
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@ -4309,6 +4311,7 @@ struct qla_hw_data {
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#define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
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/* Cisco fabric attached */
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#define FW_ATTR_EXT0_SCM_CISCO 0x00002000
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#define FW_ATTR_EXT0_NVME2 BIT_13
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uint16_t fw_attributes_ext[2];
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uint32_t fw_memory_size;
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uint32_t fw_transfer_size;
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@ -4658,6 +4661,7 @@ typedef struct scsi_qla_host {
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uint32_t qpairs_rsp_created:1;
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uint32_t nvme_enabled:1;
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uint32_t nvme_first_burst:1;
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uint32_t nvme2_enabled:1;
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} flags;
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atomic_t loop_state;
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@ -2378,6 +2378,14 @@ qla24xx_prli_iocb(srb_t *sp, struct logio_entry_24xx *logio)
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if (sp->vha->flags.nvme_first_burst)
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logio->io_parameter[0] =
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cpu_to_le32(NVME_PRLI_SP_FIRST_BURST);
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if (sp->vha->flags.nvme2_enabled) {
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/* Set service parameter BIT_8 for SLER support */
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logio->io_parameter[0] |=
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cpu_to_le32(NVME_PRLI_SP_SLER);
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/* Set service parameter BIT_9 for PI control support */
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logio->io_parameter[0] |=
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cpu_to_le32(NVME_PRLI_SP_PI_CTRL);
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}
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}
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logio->nport_handle = cpu_to_le16(sp->fcport->loop_id);
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@ -1093,6 +1093,14 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha)
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"%s: FC-NVMe is Enabled (0x%x)\n",
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__func__, ha->fw_attributes_h);
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}
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/* BIT_13 of Extended FW Attributes informs about NVMe2 support */
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if (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_NVME2) {
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ql_log(ql_log_info, vha, 0xd302,
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"Firmware supports NVMe2 0x%x\n",
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ha->fw_attributes_ext[0]);
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vha->flags.nvme2_enabled = 1;
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}
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}
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if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
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@ -1122,12 +1130,18 @@ qla2x00_get_fw_version(scsi_qla_host_t *vha)
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if (ha->flags.scm_supported_a &&
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(ha->fw_attributes_ext[0] & FW_ATTR_EXT0_SCM_SUPPORTED)) {
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ha->flags.scm_supported_f = 1;
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memset(ha->sf_init_cb, 0, sizeof(struct init_sf_cb));
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ha->sf_init_cb->flags |= BIT_13;
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}
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ql_log(ql_log_info, vha, 0x11a3, "SCM in FW: %s\n",
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(ha->flags.scm_supported_f) ? "Supported" :
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"Not Supported");
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if (vha->flags.nvme2_enabled) {
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/* set BIT_15 of special feature control block for SLER */
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ha->sf_init_cb->flags |= BIT_15;
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/* set BIT_14 of special feature control block for PI CTRL*/
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ha->sf_init_cb->flags |= BIT_14;
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}
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}
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failed:
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@ -1823,7 +1837,7 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
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mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
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}
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if (ha->flags.scm_supported_f) {
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if (ha->flags.scm_supported_f || vha->flags.nvme2_enabled) {
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mcp->mb[1] |= BIT_1;
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mcp->mb[16] = MSW(ha->sf_init_cb_dma);
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mcp->mb[17] = LSW(ha->sf_init_cb_dma);
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@ -69,6 +69,14 @@ int qla_nvme_register_remote(struct scsi_qla_host *vha, struct fc_port *fcport)
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return ret;
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}
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if (fcport->nvme_prli_service_param & NVME_PRLI_SP_SLER)
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ql_log(ql_log_info, vha, 0x212a,
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"PortID:%06x Supports SLER\n", req.port_id);
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if (fcport->nvme_prli_service_param & NVME_PRLI_SP_PI_CTRL)
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ql_log(ql_log_info, vha, 0x212b,
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"PortID:%06x Supports PI control\n", req.port_id);
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rport = fcport->nvme_remote_port->private;
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rport->fcport = fcport;
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@ -368,6 +376,7 @@ static inline int qla2x00_start_nvme_mq(srb_t *sp)
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struct srb_iocb *nvme = &sp->u.iocb_cmd;
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struct scatterlist *sgl, *sg;
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struct nvmefc_fcp_req *fd = nvme->u.nvme.desc;
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struct nvme_fc_cmd_iu *cmd = fd->cmdaddr;
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uint32_t rval = QLA_SUCCESS;
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/* Setup qpair pointers */
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@ -399,8 +408,6 @@ static inline int qla2x00_start_nvme_mq(srb_t *sp)
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}
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if (unlikely(!fd->sqid)) {
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struct nvme_fc_cmd_iu *cmd = fd->cmdaddr;
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if (cmd->sqe.common.opcode == nvme_admin_async_event) {
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nvme->u.nvme.aen_op = 1;
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atomic_inc(&ha->nvme_active_aen_cnt);
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@ -446,6 +453,11 @@ static inline int qla2x00_start_nvme_mq(srb_t *sp)
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} else if (fd->io_dir == 0) {
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cmd_pkt->control_flags = 0;
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}
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/* Set BIT_13 of control flags for Async event */
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if (vha->flags.nvme2_enabled &&
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cmd->sqe.common.opcode == nvme_admin_async_event) {
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cmd_pkt->control_flags |= cpu_to_le16(CF_ADMIN_ASYNC_EVENT);
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}
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/* Set NPORT-ID */
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cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id);
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@ -54,6 +54,7 @@ struct cmd_nvme {
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uint64_t rsvd;
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__le16 control_flags; /* Control Flags */
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#define CF_ADMIN_ASYNC_EVENT BIT_13
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#define CF_NVME_FIRST_BURST_ENABLE BIT_11
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#define CF_DIF_SEG_DESCR_ENABLE BIT_3
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#define CF_DATA_SEG_DESCR_ENABLE BIT_2
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@ -4231,6 +4231,7 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
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&ha->sf_init_cb_dma);
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if (!ha->sf_init_cb)
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goto fail_sf_init_cb;
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memset(ha->sf_init_cb, 0, sizeof(struct init_sf_cb));
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ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
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"sf_init_cb=%p.\n", ha->sf_init_cb);
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}
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