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drm/amd/display: Check DCN PState ASSERT failure 

[Description] ASIC change debug register definition

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hersen Wu 2018-02-13 16:23:12 -05:00 committed by Alex Deucher
parent 3d53f42479
commit cf1df90f35
2 changed files with 7 additions and 3 deletions
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9
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
View File

@ -100,7 +100,6 @@ bool hubbub1_verify_allow_pstate_change_high(
static unsigned int max_sampled_pstate_wait_us; /* data collection */
static bool forced_pstate_allow; /* help with revert wa */
unsigned int debug_index = 0x7;
unsigned int debug_data;
unsigned int i;
@ -115,7 +114,9 @@ bool hubbub1_verify_allow_pstate_change_high(
forced_pstate_allow = false;
}
/* description "3-0: Pipe0 cursor0 QOS
/* RV1:
* dchubbubdebugind, at: 0x7
* description "3-0: Pipe0 cursor0 QOS
* 7-4: Pipe1 cursor0 QOS
* 11-8: Pipe2 cursor0 QOS
* 15-12: Pipe3 cursor0 QOS
@ -137,7 +138,8 @@ bool hubbub1_verify_allow_pstate_change_high(
* 31: SOC pstate change request
*/
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, debug_index);
REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate);
for (i = 0; i < pstate_wait_timeout_us; i++) {
debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
@ -512,5 +514,6 @@ void hubbub1_construct(struct hubbub *hubbub,
hubbub->shifts = hubbub_shift;
hubbub->masks = hubbub_mask;
hubbub->debug_test_index_pstate = 0x7;
}

1
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
View File

@ -185,6 +185,7 @@ struct hubbub {
const struct dcn_hubbub_registers *regs;
const struct dcn_hubbub_shift *shifts;
const struct dcn_hubbub_mask *masks;
unsigned int debug_test_index_pstate;
};
void hubbub1_update_dchub(