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Pin control fixes for the v5.7 series: 

- Pad lock register on Intel Sunrisepoint had the wrong offset.
 - Fix pin config setting for the Baytrail GPIO chip.
 - Fix a compilation warning in the Mediatek driver.
 - Fix a function group name in the Actions driver.
 - Fix a behaviour bug in the edge polarity code in the Qualcomm
   driver.
 - Add a missing spinlock in the Intel Cherryview driver.
 - Add affinity callbacks to the Qualcomm MSMGPIO chip.
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Merge tag 'pinctrl-v5.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "A bunch of pin control fixes, some a bit overly ripe, sorry about
  that. We have important systems like Intel laptops and Qualcomm mobile
  chips covered.

   - Pad lock register on Intel Sunrisepoint had the wrong offset

   - Fix pin config setting for the Baytrail GPIO chip

   - Fix a compilation warning in the Mediatek driver

   - Fix a function group name in the Actions driver

   - Fix a behaviour bug in the edge polarity code in the Qualcomm
     driver

   - Add a missing spinlock in the Intel Cherryview driver

   - Add affinity callbacks to the Qualcomm MSMGPIO chip"

* tag 'pinctrl-v5.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: qcom: Add affinity callbacks to msmgpio IRQ chip
  pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler
  pinctrl: qcom: fix wrong write in update_dual_edge
  pinctrl: actions: fix function group name for i2c0_group
  pinctrl: mediatek: remove shadow variable declaration
  pinctrl: baytrail: Enable pin configuration setting for GPIO chip
  pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H
This commit is contained in:
Linus Torvalds 2020-05-16 13:20:50 -07:00
parent 18e70f3a76 dca4f40742
commit cf0ca701a0
6 changed files with 40 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/pinctrl/actions/pinctrl-s700.c
View File

@ -1435,7 +1435,7 @@ static const char * const sd2_groups[] = {
static const char * const i2c0_groups[] = {
"uart0_rx_mfp",
"uart0_tx_mfp",
"i2c0_mfp_mfp",
"i2c0_mfp",
};
static const char * const i2c1_groups[] = {

1
drivers/pinctrl/intel/pinctrl-baytrail.c
View File

@ -1286,6 +1286,7 @@ static const struct gpio_chip byt_gpio_chip = {
.direction_output = byt_gpio_direction_output,
.get = byt_gpio_get,
.set = byt_gpio_set,
.set_config = gpiochip_generic_config,
.dbg_show = byt_gpio_dbg_show,
};

4
drivers/pinctrl/intel/pinctrl-cherryview.c
View File

@ -1479,11 +1479,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
unsigned long flags;
u32 intr_line;
chained_irq_enter(chip, desc);
raw_spin_lock_irqsave(&chv_lock, flags);
pending = readl(pctrl->regs + CHV_INTSTAT);
raw_spin_unlock_irqrestore(&chv_lock, flags);
for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
unsigned int irq, offset;

15
drivers/pinctrl/intel/pinctrl-sunrisepoint.c
View File

@ -15,17 +15,18 @@
#include "pinctrl-intel.h"
#define SPT_PAD_OWN 0x020
#define SPT_PADCFGLOCK 0x0a0
#define SPT_HOSTSW_OWN 0x0d0
#define SPT_GPI_IS 0x100
#define SPT_GPI_IE 0x120
#define SPT_PAD_OWN 0x020
#define SPT_H_PADCFGLOCK 0x090
#define SPT_LP_PADCFGLOCK 0x0a0
#define SPT_HOSTSW_OWN 0x0d0
#define SPT_GPI_IS 0x100
#define SPT_GPI_IE 0x120
#define SPT_COMMUNITY(b, s, e) \
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_PADCFGLOCK, \
.padcfglock_offset = SPT_LP_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \
@ -47,7 +48,7 @@
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
.padcfglock_offset = SPT_PADCFGLOCK, \
.padcfglock_offset = SPT_H_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \

2
drivers/pinctrl/mediatek/pinctrl-paris.c
View File

@ -164,8 +164,6 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
case MTK_PIN_CONFIG_PU_ADV:
case MTK_PIN_CONFIG_PD_ADV:
if (hw->soc->adv_pull_get) {
bool pullup;
pullup = param == MTK_PIN_CONFIG_PU_ADV;
err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
} else

27
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -697,7 +697,7 @@ static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
pol = msm_readl_intr_cfg(pctrl, g);
pol ^= BIT(g->intr_polarity_bit);
msm_writel_intr_cfg(val, pctrl, g);
msm_writel_intr_cfg(pol, pctrl, g);
val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
intstat = msm_readl_intr_status(pctrl, g);
@ -1034,6 +1034,29 @@ static void msm_gpio_irq_relres(struct irq_data *d)
module_put(gc->owner);
}
static int msm_gpio_irq_set_affinity(struct irq_data *d,
const struct cpumask *dest, bool force)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
return irq_chip_set_affinity_parent(d, dest, force);
return 0;
}
static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
return 0;
}
static void msm_gpio_irq_handler(struct irq_desc *desc)
{
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
@ -1132,6 +1155,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
if (np) {