arm64: dts: rockchip: add rk3368 iommu nodes
Add IEP/ISP/VOP/HEVC/VPU iommu nodes Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -805,6 +805,55 @@
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status = "disabled";
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};
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iep_mmu: iommu@ff900800 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff900800 0x0 0x100>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "iep_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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isp_mmu: iommu@ff914000 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff914000 0x0 0x100>,
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<0x0 0xff915000 0x0 0x100>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "isp_mmu";
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#iommu-cells = <0>;
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rockchip,disable-mmu-reset;
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status = "disabled";
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};
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vop_mmu: iommu@ff930300 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff930300 0x0 0x100>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vop_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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hevc_mmu: iommu@ff9a0440 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff9a0440 0x0 0x40>,
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<0x0 0xff9a0480 0x0 0x40>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hevc_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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vpu_mmu: iommu@ff9a0800 {
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compatible = "rockchip,iommu";
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reg = <0x0 0xff9a0800 0x0 0x100>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vepu_mmu", "vdpu_mmu";
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#iommu-cells = <0>;
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status = "disabled";
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};
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gic: interrupt-controller@ffb71000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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