sh: pci: Use I/O accessors consistently in SH7786 PCIe init code.
Some of the existing code is flipping between __raw_xxx() and pci_{read,write}_reg(). As the latter are just wrappers for the former, flip over to using them consistently. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -304,24 +304,24 @@ static int pcie_init(struct sh7786_pcie_port *port)
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* LAR1/LAMR1.
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* LAR1/LAMR1.
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*/
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*/
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if (memsize > SZ_512M) {
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if (memsize > SZ_512M) {
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__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
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pci_write_reg(chan, memphys + SZ_512M, SH4A_PCIELAR1);
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__raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
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pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
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chan->reg_base + SH4A_PCIELAMR1);
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SH4A_PCIELAMR1);
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memsize = SZ_512M;
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memsize = SZ_512M;
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} else {
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} else {
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/*
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/*
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* Otherwise just zero it out and disable it.
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* Otherwise just zero it out and disable it.
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*/
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*/
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__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
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pci_write_reg(chan, 0, SH4A_PCIELAR1);
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__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
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pci_write_reg(chan, 0, SH4A_PCIELAMR1);
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}
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}
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/*
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/*
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* LAR0/LAMR0 covers up to the first 512MB, which is enough to
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* LAR0/LAMR0 covers up to the first 512MB, which is enough to
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* cover all of lowmem on most platforms.
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* cover all of lowmem on most platforms.
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*/
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*/
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__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
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pci_write_reg(chan, memphys, SH4A_PCIELAR0);
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__raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
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pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
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/* Finish initialization */
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/* Finish initialization */
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data = pci_read_reg(chan, SH4A_PCIETCTLR);
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data = pci_read_reg(chan, SH4A_PCIETCTLR);
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@ -370,7 +370,7 @@ static int pcie_init(struct sh7786_pcie_port *port)
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for (i = win = 0; i < chan->nr_resources; i++) {
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for (i = win = 0; i < chan->nr_resources; i++) {
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struct resource *res = chan->resources + i;
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struct resource *res = chan->resources + i;
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resource_size_t size;
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resource_size_t size;
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u32 enable_mask;
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u32 mask;
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/*
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/*
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* We can't use the 32-bit mode windows in legacy 29-bit
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* We can't use the 32-bit mode windows in legacy 29-bit
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@ -381,23 +381,24 @@ static int pcie_init(struct sh7786_pcie_port *port)
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
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size = resource_size(res);
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/*
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/*
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* The PAMR mask is calculated in units of 256kB, which
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* The PAMR mask is calculated in units of 256kB, which
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* keeps things pretty simple.
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* keeps things pretty simple.
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*/
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*/
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__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
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size = resource_size(res);
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chan->reg_base + SH4A_PCIEPAMR(win));
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mask = (roundup_pow_of_two(size) / SZ_256K) - 1;
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pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));
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pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
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pci_write_reg(chan, RES_TO_U32_HIGH(res->start),
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
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SH4A_PCIEPARH(win));
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pci_write_reg(chan, RES_TO_U32_LOW(res->start),
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SH4A_PCIEPARL(win));
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enable_mask = MASK_PARE;
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mask = MASK_PARE;
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if (res->flags & IORESOURCE_IO)
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if (res->flags & IORESOURCE_IO)
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enable_mask |= MASK_SPC;
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mask |= MASK_SPC;
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pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
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pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));
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win++;
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win++;
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}
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}
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@ -568,6 +568,13 @@
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#define PCI_REG(x) ((x) + 0x40000)
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#define PCI_REG(x) ((x) + 0x40000)
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#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
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#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
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#define RES_TO_U32_LOW(val) \
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((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
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#define RES_TO_U32_HIGH(val) \
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((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
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static inline void
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static inline void
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pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg)
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pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg)
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{
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{
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