pwm: Changes for v5.2-rc1
Nothing out of the ordinary this cycle. The bulk of this is a collection of fixes for existing drivers and some cleanups. There's one new driver for i.MX SoCs and addition of support for some new variants to existing drivers. -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlzVW/MZHHRoaWVycnku cmVkaW5nQGdtYWlsLmNvbQAKCRDdI6zXfz6zoVgJEACIqcHeP5SrGv+Bh5xoAsNL HNLu72QOTVFYICBPSTqsS9QgGvkeZErv86dheYp6MSJHuRCGu/d4Vlp6iY8YmiS0 i3Vi9Ib8sGsbC2kKJSsLnAO7d1JrDkyxYS8sSGSR0G2xKZA1dgXVqtAEdOubUU0x /HrzpP8uSoSiKflEfGtU3OykAdY8b1UBtWuC+KxVP2z5A2IAJchYQcXQ3v+kVbvT Jp+mYbYfViwb40JKFkg67hm7y494LFAMZhInzv5ImQXl1ji+C2VPGfqBdlxwgW8g +OyP0Conh6oHlEB4Wc7xfWec0PYJee9hNlXR30L+a1OCTisnOq7aHHjf6+ej7NDq KeQPEt9r8URgRMbfPvL70TRk46QeToeC07BO7aEGK3gd2C2c6ZoFmyhhauM6j2z0 eL8xK7WnynKCUrQ0tgQhv8AZkZE/Hp2ddgicyu0ARECugRiqd/uVNeip3M3TkPmV Zv0nRZzhFUk+t0DNX6krEVzvkaFznzWGDK6PGeHHbNdR58GaRnYzM0WXytYqUNGa +kryN/sj0vgzVj+ATxvDfVYqAtZMYcXvZMJQhfjNAPP89F3lHrsONf6pvD++azOM 8HugNF01zR0uZ2Z/JXPL5mZxybYlCBQdmK6QxEB+YcmJizCcnOCsWoEi1XVOGyCC /alcvvLa2DceO1lJIo0o7g== =3p6h -----END PGP SIGNATURE----- Merge tag 'pwm/for-5.2-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "Nothing out of the ordinary this cycle. The bulk of this is a collection of fixes for existing drivers and some cleanups. There's one new driver for i.MX SoCs and addition of support for some new variants to existing drivers" * tag 'pwm/for-5.2-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: meson: Add clock source configuration for Meson G12A dt-bindings: pwm: Update bindings for the Meson G12A Family pwm: samsung: Don't uses devm_*() functions in ->request() pwm: Clear chip_data in pwm_put() pwm: Add i.MX TPM PWM driver support dt-bindings: pwm: Add i.MX TPM PWM binding pwm: imx27: Use devm_platform_ioremap_resource() to simplify code pwm: meson: Use the spin-lock only to protect register modifications pwm: meson: Don't disable PWM when setting duty repeatedly pwm: meson: Consider 128 a valid pre-divider pwm: sysfs: fix typo "its" -> "it's" pwm: tiehrpwm: Enable compilation for ARCH_K3 dt-bindings: pwm: tiehrpwm: Add TI AM654 SoC specific compatible pwm: tiehrpwm: Update shadow register for disabling PWMs pwm: img: Turn final 'else if' into 'else' in img_pwm_config pwm: Fix deadlock warning when removing PWM device
This commit is contained in:
Linus Torvalds
commit
cece6460c2
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@ -0,0 +1,22 @@
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Freescale i.MX TPM PWM controller
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Required properties:
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- compatible : Should be "fsl,imx7ulp-pwm".
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- reg: Physical base address and length of the controller's registers.
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- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of the cells format.
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- clocks : The clock provided by the SoC to drive the PWM.
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- interrupts: The interrupt for the PWM controller.
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Note: The TPM counter and period counter are shared between multiple channels, so all channels
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should use same period setting.
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Example:
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tpm4: pwm@40250000 {
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compatible = "fsl,imx7ulp-pwm";
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reg = <0x40250000 0x1000>;
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assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
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clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
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#pwm-cells = <3>;
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};
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@ -7,6 +7,9 @@ Required properties:
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or "amlogic,meson-gxbb-ao-pwm"
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or "amlogic,meson-axg-ee-pwm"
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or "amlogic,meson-axg-ao-pwm"
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or "amlogic,meson-g12a-ee-pwm"
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or "amlogic,meson-g12a-ao-pwm-ab"
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or "amlogic,meson-g12a-ao-pwm-cd"
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- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
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the cells format.
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@ -4,6 +4,7 @@ Required properties:
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- compatible: Must be "ti,<soc>-ehrpwm".
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for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
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for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
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for am654 - compatible = "ti,am654-ehrpwm", "ti-am3352-ehrpwm";
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for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
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for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
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- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
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@ -210,6 +210,17 @@ config PWM_IMX27
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To compile this driver as a module, choose M here: the module
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will be called pwm-imx27.
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config PWM_IMX_TPM
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tristate "i.MX TPM PWM support"
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depends on ARCH_MXC || COMPILE_TEST
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depends on HAVE_CLK && HAS_IOMEM
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help
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Generic PWM framework driver for i.MX7ULP TPM module, TPM's full
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name is Low Power Timer/Pulse Width Modulation Module.
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To compile this driver as a module, choose M here: the module
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will be called pwm-imx-tpm.
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config PWM_JZ4740
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tristate "Ingenic JZ47xx PWM support"
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depends on MACH_INGENIC
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@ -467,10 +478,9 @@ config PWM_TIECAP
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config PWM_TIEHRPWM
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tristate "EHRPWM PWM support"
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depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX
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depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX || ARCH_K3
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help
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PWM driver support for the EHRPWM controller found on AM33XX
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TI SOC
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PWM driver support for the EHRPWM controller found on TI SOCs
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To compile this driver as a module, choose M here: the module
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will be called pwm-tiehrpwm.
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@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o
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obj-$(CONFIG_PWM_IMG) += pwm-img.o
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obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
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obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o
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obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o
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obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
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obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o
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obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o
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@ -311,10 +311,12 @@ int pwmchip_add_with_polarity(struct pwm_chip *chip,
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if (IS_ENABLED(CONFIG_OF))
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of_pwmchip_add(chip);
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pwmchip_sysfs_export(chip);
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out:
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mutex_unlock(&pwm_lock);
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if (!ret)
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pwmchip_sysfs_export(chip);
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return ret;
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}
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EXPORT_SYMBOL_GPL(pwmchip_add_with_polarity);
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@ -348,7 +350,7 @@ int pwmchip_remove(struct pwm_chip *chip)
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unsigned int i;
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int ret = 0;
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pwmchip_sysfs_unexport_children(chip);
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pwmchip_sysfs_unexport(chip);
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mutex_lock(&pwm_lock);
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@ -368,8 +370,6 @@ int pwmchip_remove(struct pwm_chip *chip)
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free_pwms(chip);
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pwmchip_sysfs_unexport(chip);
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out:
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mutex_unlock(&pwm_lock);
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return ret;
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@ -877,6 +877,7 @@ void pwm_put(struct pwm_device *pwm)
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if (pwm->chip->ops->free)
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pwm->chip->ops->free(pwm->chip, pwm);
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pwm_set_chip_data(pwm, NULL);
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pwm->label = NULL;
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module_put(pwm->chip->ops->owner);
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@ -84,7 +84,6 @@ static void berlin_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct berlin_pwm_channel *channel = pwm_get_chip_data(pwm);
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pwm_set_chip_data(pwm, NULL);
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kfree(channel);
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}
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@ -123,7 +123,7 @@ static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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} else if (mul <= max_timebase * 512) {
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div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
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timebase = DIV_ROUND_UP(mul, 512);
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} else if (mul > max_timebase * 512) {
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} else {
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dev_err(chip->dev,
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"failed to configure timebase steps/divider value\n");
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return -EINVAL;
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@ -0,0 +1,449 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2018-2019 NXP.
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*
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* Limitations:
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* - The TPM counter and period counter are shared between
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* multiple channels, so all channels should use same period
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* settings.
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* - Changes to polarity cannot be latched at the time of the
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* next period start.
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* - Changing period and duty cycle together isn't atomic,
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* with the wrong timing it might happen that a period is
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* produced with old duty cycle but new period settings.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#define PWM_IMX_TPM_PARAM 0x4
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#define PWM_IMX_TPM_GLOBAL 0x8
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#define PWM_IMX_TPM_SC 0x10
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#define PWM_IMX_TPM_CNT 0x14
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#define PWM_IMX_TPM_MOD 0x18
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#define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8)
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#define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8)
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#define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0)
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#define PWM_IMX_TPM_SC_PS GENMASK(2, 0)
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#define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3)
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#define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1)
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#define PWM_IMX_TPM_SC_CPWMS BIT(5)
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#define PWM_IMX_TPM_CnSC_CHF BIT(7)
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#define PWM_IMX_TPM_CnSC_MSB BIT(5)
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#define PWM_IMX_TPM_CnSC_MSA BIT(4)
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/*
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* The reference manual describes this field as two separate bits. The
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* semantic of the two bits isn't orthogonal though, so they are treated
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* together as a 2-bit field here.
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*/
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#define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2)
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#define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1)
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#define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2)
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#define PWM_IMX_TPM_MOD_WIDTH 16
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#define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0)
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struct imx_tpm_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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struct mutex lock;
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u32 user_count;
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u32 enable_count;
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u32 real_period;
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};
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struct imx_tpm_pwm_param {
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u8 prescale;
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u32 mod;
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u32 val;
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};
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static inline struct imx_tpm_pwm_chip *
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to_imx_tpm_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct imx_tpm_pwm_chip, chip);
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}
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/*
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* This function determines for a given pwm_state *state that a consumer
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* might request the pwm_state *real_state that eventually is implemented
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* by the hardware and the necessary register values (in *p) to achieve
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* this.
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*/
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static int pwm_imx_tpm_round_state(struct pwm_chip *chip,
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struct imx_tpm_pwm_param *p,
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struct pwm_state *real_state,
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struct pwm_state *state)
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{
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struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
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u32 rate, prescale, period_count, clock_unit;
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u64 tmp;
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rate = clk_get_rate(tpm->clk);
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tmp = (u64)state->period * rate;
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clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC);
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if (clock_unit <= PWM_IMX_TPM_MOD_MOD)
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prescale = 0;
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else
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prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH;
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if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale)))
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return -ERANGE;
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p->prescale = prescale;
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period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale;
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p->mod = period_count;
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/* calculate real period HW can support */
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tmp = (u64)period_count << prescale;
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tmp *= NSEC_PER_SEC;
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real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);
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/*
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* if eventually the PWM output is inactive, either
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* duty cycle is 0 or status is disabled, need to
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* make sure the output pin is inactive.
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*/
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if (!state->enabled)
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real_state->duty_cycle = 0;
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else
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real_state->duty_cycle = state->duty_cycle;
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tmp = (u64)p->mod * real_state->duty_cycle;
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p->val = DIV_ROUND_CLOSEST_ULL(tmp, real_state->period);
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real_state->polarity = state->polarity;
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real_state->enabled = state->enabled;
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return 0;
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}
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static void pwm_imx_tpm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
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u32 rate, val, prescale;
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u64 tmp;
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/* get period */
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state->period = tpm->real_period;
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/* get duty cycle */
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rate = clk_get_rate(tpm->clk);
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val = readl(tpm->base + PWM_IMX_TPM_SC);
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prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
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tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
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tmp = (tmp << prescale) * NSEC_PER_SEC;
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);
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/* get polarity */
|
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val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
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if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED)
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state->polarity = PWM_POLARITY_INVERSED;
|
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else
|
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/*
|
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* Assume reserved values (2b00 and 2b11) to yield
|
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* normal polarity.
|
||||
*/
|
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state->polarity = PWM_POLARITY_NORMAL;
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|
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/* get channel status */
|
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state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false;
|
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}
|
||||
|
||||
/* this function is supposed to be called with mutex hold */
|
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static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip,
|
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struct imx_tpm_pwm_param *p,
|
||||
struct pwm_state *state,
|
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struct pwm_device *pwm)
|
||||
{
|
||||
struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
|
||||
bool period_update = false;
|
||||
bool duty_update = false;
|
||||
u32 val, cmod, cur_prescale;
|
||||
unsigned long timeout;
|
||||
struct pwm_state c;
|
||||
|
||||
if (state->period != tpm->real_period) {
|
||||
/*
|
||||
* TPM counter is shared by multiple channels, so
|
||||
* prescale and period can NOT be modified when
|
||||
* there are multiple channels in use with different
|
||||
* period settings.
|
||||
*/
|
||||
if (tpm->user_count > 1)
|
||||
return -EBUSY;
|
||||
|
||||
val = readl(tpm->base + PWM_IMX_TPM_SC);
|
||||
cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val);
|
||||
cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val);
|
||||
if (cmod && cur_prescale != p->prescale)
|
||||
return -EBUSY;
|
||||
|
||||
/* set TPM counter prescale */
|
||||
val &= ~PWM_IMX_TPM_SC_PS;
|
||||
val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale);
|
||||
writel(val, tpm->base + PWM_IMX_TPM_SC);
|
||||
|
||||
/*
|
||||
* set period count:
|
||||
* if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register
|
||||
* is updated when MOD register is written.
|
||||
*
|
||||
* if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length
|
||||
* is latched into hardware when the next period starts.
|
||||
*/
|
||||
writel(p->mod, tpm->base + PWM_IMX_TPM_MOD);
|
||||
tpm->real_period = state->period;
|
||||
period_update = true;
|
||||
}
|
||||
|
||||
pwm_imx_tpm_get_state(chip, pwm, &c);
|
||||
|
||||
/* polarity is NOT allowed to be changed if PWM is active */
|
||||
if (c.enabled && c.polarity != state->polarity)
|
||||
return -EBUSY;
|
||||
|
||||
if (state->duty_cycle != c.duty_cycle) {
|
||||
/*
|
||||
* set channel value:
|
||||
* if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register
|
||||
* is updated when CnV register is written.
|
||||
*
|
||||
* if the PWM is enabled (CMOD[1:0] ≠ 2b00), the duty length
|
||||
* is latched into hardware when the next period starts.
|
||||
*/
|
||||
writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm));
|
||||
duty_update = true;
|
||||
}
|
||||
|
||||
/* make sure MOD & CnV registers are updated */
|
||||
if (period_update || duty_update) {
|
||||
timeout = jiffies + msecs_to_jiffies(tpm->real_period /
|
||||
NSEC_PER_MSEC + 1);
|
||||
while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod
|
||||
|| readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm))
|
||||
!= p->val) {
|
||||
if (time_after(jiffies, timeout))
|
||||
return -ETIME;
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* polarity settings will enabled/disable output status
|
||||
* immediately, so if the channel is disabled, need to
|
||||
* make sure MSA/MSB/ELS are set to 0 which means channel
|
||||
* disabled.
|
||||
*/
|
||||
val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
|
||||
val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA |
|
||||
PWM_IMX_TPM_CnSC_MSB);
|
||||
if (state->enabled) {
|
||||
/*
|
||||
* set polarity (for edge-aligned PWM modes)
|
||||
*
|
||||
* ELS[1:0] = 2b10 yields normal polarity behaviour,
|
||||
* ELS[1:0] = 2b01 yields inversed polarity.
|
||||
* The other values are reserved.
|
||||
*/
|
||||
val |= PWM_IMX_TPM_CnSC_MSB;
|
||||
val |= (state->polarity == PWM_POLARITY_NORMAL) ?
|
||||
PWM_IMX_TPM_CnSC_ELS_NORMAL :
|
||||
PWM_IMX_TPM_CnSC_ELS_INVERSED;
|
||||
}
|
||||
writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm));
|
||||
|
||||
/* control the counter status */
|
||||
if (state->enabled != c.enabled) {
|
||||
val = readl(tpm->base + PWM_IMX_TPM_SC);
|
||||
if (state->enabled) {
|
||||
if (++tpm->enable_count == 1)
|
||||
val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK;
|
||||
} else {
|
||||
if (--tpm->enable_count == 0)
|
||||
val &= ~PWM_IMX_TPM_SC_CMOD;
|
||||
}
|
||||
writel(val, tpm->base + PWM_IMX_TPM_SC);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pwm_imx_tpm_apply(struct pwm_chip *chip,
|
||||
struct pwm_device *pwm,
|
||||
struct pwm_state *state)
|
||||
{
|
||||
struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
|
||||
struct imx_tpm_pwm_param param;
|
||||
struct pwm_state real_state;
|
||||
int ret;
|
||||
|
||||
ret = pwm_imx_tpm_round_state(chip, ¶m, &real_state, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mutex_lock(&tpm->lock);
|
||||
ret = pwm_imx_tpm_apply_hw(chip, ¶m, &real_state, pwm);
|
||||
mutex_unlock(&tpm->lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
|
||||
|
||||
mutex_lock(&tpm->lock);
|
||||
tpm->user_count++;
|
||||
mutex_unlock(&tpm->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip);
|
||||
|
||||
mutex_lock(&tpm->lock);
|
||||
tpm->user_count--;
|
||||
mutex_unlock(&tpm->lock);
|
||||
}
|
||||
|
||||
static const struct pwm_ops imx_tpm_pwm_ops = {
|
||||
.request = pwm_imx_tpm_request,
|
||||
.free = pwm_imx_tpm_free,
|
||||
.get_state = pwm_imx_tpm_get_state,
|
||||
.apply = pwm_imx_tpm_apply,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int pwm_imx_tpm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct imx_tpm_pwm_chip *tpm;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
tpm = devm_kzalloc(&pdev->dev, sizeof(*tpm), GFP_KERNEL);
|
||||
if (!tpm)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, tpm);
|
||||
|
||||
tpm->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(tpm->base))
|
||||
return PTR_ERR(tpm->base);
|
||||
|
||||
tpm->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(tpm->clk)) {
|
||||
ret = PTR_ERR(tpm->clk);
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(&pdev->dev,
|
||||
"failed to get PWM clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(tpm->clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to prepare or enable clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
tpm->chip.dev = &pdev->dev;
|
||||
tpm->chip.ops = &imx_tpm_pwm_ops;
|
||||
tpm->chip.base = -1;
|
||||
tpm->chip.of_xlate = of_pwm_xlate_with_flags;
|
||||
tpm->chip.of_pwm_n_cells = 3;
|
||||
|
||||
/* get number of channels */
|
||||
val = readl(tpm->base + PWM_IMX_TPM_PARAM);
|
||||
tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val);
|
||||
|
||||
mutex_init(&tpm->lock);
|
||||
|
||||
ret = pwmchip_add(&tpm->chip);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
|
||||
clk_disable_unprepare(tpm->clk);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pwm_imx_tpm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct imx_tpm_pwm_chip *tpm = platform_get_drvdata(pdev);
|
||||
int ret = pwmchip_remove(&tpm->chip);
|
||||
|
||||
clk_disable_unprepare(tpm->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __maybe_unused pwm_imx_tpm_suspend(struct device *dev)
|
||||
{
|
||||
struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
|
||||
|
||||
if (tpm->enable_count > 0)
|
||||
return -EBUSY;
|
||||
|
||||
clk_disable_unprepare(tpm->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused pwm_imx_tpm_resume(struct device *dev)
|
||||
{
|
||||
struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = clk_prepare_enable(tpm->clk);
|
||||
if (ret)
|
||||
dev_err(dev,
|
||||
"failed to prepare or enable clock: %d\n",
|
||||
ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm,
|
||||
pwm_imx_tpm_suspend, pwm_imx_tpm_resume);
|
||||
|
||||
static const struct of_device_id imx_tpm_pwm_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx7ulp-pwm", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids);
|
||||
|
||||
static struct platform_driver imx_tpm_pwm_driver = {
|
||||
.driver = {
|
||||
.name = "imx7ulp-tpm-pwm",
|
||||
.of_match_table = imx_tpm_pwm_dt_ids,
|
||||
.pm = &imx_tpm_pwm_pm,
|
||||
},
|
||||
.probe = pwm_imx_tpm_probe,
|
||||
.remove = pwm_imx_tpm_remove,
|
||||
};
|
||||
module_platform_driver(imx_tpm_pwm_driver);
|
||||
|
||||
MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
|
||||
MODULE_DESCRIPTION("i.MX TPM PWM Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -291,7 +291,6 @@ MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids);
|
|||
static int pwm_imx27_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct pwm_imx27_chip *imx;
|
||||
struct resource *r;
|
||||
|
||||
imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
|
||||
if (imx == NULL)
|
||||
|
|
@ -326,8 +325,7 @@ static int pwm_imx27_probe(struct platform_device *pdev)
|
|||
imx->chip.of_xlate = of_pwm_xlate_with_flags;
|
||||
imx->chip.of_pwm_n_cells = 3;
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
|
||||
imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(imx->mmio_base))
|
||||
return PTR_ERR(imx->mmio_base);
|
||||
|
||||
|
|
|
|||
|
|
@ -111,6 +111,10 @@ struct meson_pwm {
|
|||
const struct meson_pwm_data *data;
|
||||
void __iomem *base;
|
||||
u8 inverter_mask;
|
||||
/*
|
||||
* Protects register (write) access to the REG_MISC_AB register
|
||||
* that is shared between the two PWMs.
|
||||
*/
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
|
|
@ -184,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
|
|||
do_div(fin_ps, fin_freq);
|
||||
|
||||
/* Calc pre_div with the period */
|
||||
for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
|
||||
for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
|
||||
cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
|
||||
fin_ps * (pre_div + 1));
|
||||
dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
|
||||
|
|
@ -193,7 +197,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
|
|||
break;
|
||||
}
|
||||
|
||||
if (pre_div == MISC_CLK_DIV_MASK) {
|
||||
if (pre_div > MISC_CLK_DIV_MASK) {
|
||||
dev_err(meson->chip.dev, "unable to get period pre_div\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -235,6 +239,7 @@ static void meson_pwm_enable(struct meson_pwm *meson,
|
|||
{
|
||||
u32 value, clk_shift, clk_enable, enable;
|
||||
unsigned int offset;
|
||||
unsigned long flags;
|
||||
|
||||
switch (id) {
|
||||
case 0:
|
||||
|
|
@ -255,6 +260,8 @@ static void meson_pwm_enable(struct meson_pwm *meson,
|
|||
return;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&meson->lock, flags);
|
||||
|
||||
value = readl(meson->base + REG_MISC_AB);
|
||||
value &= ~(MISC_CLK_DIV_MASK << clk_shift);
|
||||
value |= channel->pre_div << clk_shift;
|
||||
|
|
@ -267,11 +274,14 @@ static void meson_pwm_enable(struct meson_pwm *meson,
|
|||
value = readl(meson->base + REG_MISC_AB);
|
||||
value |= enable;
|
||||
writel(value, meson->base + REG_MISC_AB);
|
||||
|
||||
spin_unlock_irqrestore(&meson->lock, flags);
|
||||
}
|
||||
|
||||
static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
|
||||
{
|
||||
u32 value, enable;
|
||||
unsigned long flags;
|
||||
|
||||
switch (id) {
|
||||
case 0:
|
||||
|
|
@ -286,9 +296,13 @@ static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id)
|
|||
return;
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&meson->lock, flags);
|
||||
|
||||
value = readl(meson->base + REG_MISC_AB);
|
||||
value &= ~enable;
|
||||
writel(value, meson->base + REG_MISC_AB);
|
||||
|
||||
spin_unlock_irqrestore(&meson->lock, flags);
|
||||
}
|
||||
|
||||
static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
|
|
@ -296,29 +310,21 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
{
|
||||
struct meson_pwm_channel *channel = pwm_get_chip_data(pwm);
|
||||
struct meson_pwm *meson = to_meson_pwm(chip);
|
||||
unsigned long flags;
|
||||
int err = 0;
|
||||
|
||||
if (!state)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&meson->lock, flags);
|
||||
|
||||
if (!state->enabled) {
|
||||
meson_pwm_disable(meson, pwm->hwpwm);
|
||||
channel->state.enabled = false;
|
||||
|
||||
goto unlock;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (state->period != channel->state.period ||
|
||||
state->duty_cycle != channel->state.duty_cycle ||
|
||||
state->polarity != channel->state.polarity) {
|
||||
if (channel->state.enabled) {
|
||||
meson_pwm_disable(meson, pwm->hwpwm);
|
||||
channel->state.enabled = false;
|
||||
}
|
||||
|
||||
if (state->polarity != channel->state.polarity) {
|
||||
if (state->polarity == PWM_POLARITY_NORMAL)
|
||||
meson->inverter_mask |= BIT(pwm->hwpwm);
|
||||
|
|
@ -329,7 +335,7 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
err = meson_pwm_calc(meson, channel, pwm->hwpwm,
|
||||
state->duty_cycle, state->period);
|
||||
if (err < 0)
|
||||
goto unlock;
|
||||
return err;
|
||||
|
||||
channel->state.polarity = state->polarity;
|
||||
channel->state.period = state->period;
|
||||
|
|
@ -341,9 +347,7 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
|
|||
channel->state.enabled = true;
|
||||
}
|
||||
|
||||
unlock:
|
||||
spin_unlock_irqrestore(&meson->lock, flags);
|
||||
return err;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
|
||||
|
|
@ -429,6 +433,24 @@ static const struct meson_pwm_data pwm_axg_ao_data = {
|
|||
.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
|
||||
};
|
||||
|
||||
static const char * const pwm_g12a_ao_cd_parent_names[] = {
|
||||
"aoclk81", "xtal",
|
||||
};
|
||||
|
||||
static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
|
||||
.parent_names = pwm_g12a_ao_cd_parent_names,
|
||||
.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names),
|
||||
};
|
||||
|
||||
static const char * const pwm_g12a_ee_parent_names[] = {
|
||||
"xtal", "hdmi_pll", "fclk_div4", "fclk_div3"
|
||||
};
|
||||
|
||||
static const struct meson_pwm_data pwm_g12a_ee_data = {
|
||||
.parent_names = pwm_g12a_ee_parent_names,
|
||||
.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names),
|
||||
};
|
||||
|
||||
static const struct of_device_id meson_pwm_matches[] = {
|
||||
{
|
||||
.compatible = "amlogic,meson8b-pwm",
|
||||
|
|
@ -450,6 +472,18 @@ static const struct of_device_id meson_pwm_matches[] = {
|
|||
.compatible = "amlogic,meson-axg-ao-pwm",
|
||||
.data = &pwm_axg_ao_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-g12a-ee-pwm",
|
||||
.data = &pwm_g12a_ee_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-g12a-ao-pwm-ab",
|
||||
.data = &pwm_axg_ao_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-g12a-ao-pwm-cd",
|
||||
.data = &pwm_g12a_ao_cd_data
|
||||
},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, meson_pwm_matches);
|
||||
|
|
|
|||
|
|
@ -176,7 +176,6 @@ static void pca9685_pwm_gpio_free(struct gpio_chip *gpio, unsigned int offset)
|
|||
pm_runtime_put(pca->chip.dev);
|
||||
mutex_lock(&pca->lock);
|
||||
pwm = &pca->chip.pwms[offset];
|
||||
pwm_set_chip_data(pwm, NULL);
|
||||
mutex_unlock(&pca->lock);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -226,7 +226,7 @@ static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL);
|
||||
our_chan = kzalloc(sizeof(*our_chan), GFP_KERNEL);
|
||||
if (!our_chan)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -237,8 +237,7 @@ static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
|
|||
|
||||
static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
{
|
||||
devm_kfree(chip->dev, pwm_get_chip_data(pwm));
|
||||
pwm_set_chip_data(pwm, NULL);
|
||||
kfree(pwm_get_chip_data(pwm));
|
||||
}
|
||||
|
||||
static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
|
||||
|
|
|
|||
|
|
@ -382,6 +382,8 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
|
|||
}
|
||||
|
||||
/* Update shadow register first before modifying active register */
|
||||
ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,
|
||||
AQSFRC_RLDCSF_ZRO);
|
||||
ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);
|
||||
/*
|
||||
* Changes to immediate action on Action Qualifier. This puts
|
||||
|
|
|
|||
|
|
@ -398,7 +398,7 @@ void pwmchip_sysfs_export(struct pwm_chip *chip)
|
|||
|
||||
/*
|
||||
* If device_create() fails the pwm_chip is still usable by
|
||||
* the kernel its just not exported.
|
||||
* the kernel it's just not exported.
|
||||
*/
|
||||
parent = device_create(&pwm_class, chip->dev, MKDEV(0, 0), chip,
|
||||
"pwmchip%d", chip->base);
|
||||
|
|
@ -409,19 +409,6 @@ void pwmchip_sysfs_export(struct pwm_chip *chip)
|
|||
}
|
||||
|
||||
void pwmchip_sysfs_unexport(struct pwm_chip *chip)
|
||||
{
|
||||
struct device *parent;
|
||||
|
||||
parent = class_find_device(&pwm_class, NULL, chip,
|
||||
pwmchip_sysfs_match);
|
||||
if (parent) {
|
||||
/* for class_find_device() */
|
||||
put_device(parent);
|
||||
device_unregister(parent);
|
||||
}
|
||||
}
|
||||
|
||||
void pwmchip_sysfs_unexport_children(struct pwm_chip *chip)
|
||||
{
|
||||
struct device *parent;
|
||||
unsigned int i;
|
||||
|
|
@ -439,6 +426,7 @@ void pwmchip_sysfs_unexport_children(struct pwm_chip *chip)
|
|||
}
|
||||
|
||||
put_device(parent);
|
||||
device_unregister(parent);
|
||||
}
|
||||
|
||||
static int __init pwm_sysfs_init(void)
|
||||
|
|
|
|||
|
|
@ -596,7 +596,6 @@ static inline void pwm_remove_table(struct pwm_lookup *table, size_t num)
|
|||
#ifdef CONFIG_PWM_SYSFS
|
||||
void pwmchip_sysfs_export(struct pwm_chip *chip);
|
||||
void pwmchip_sysfs_unexport(struct pwm_chip *chip);
|
||||
void pwmchip_sysfs_unexport_children(struct pwm_chip *chip);
|
||||
#else
|
||||
static inline void pwmchip_sysfs_export(struct pwm_chip *chip)
|
||||
{
|
||||
|
|
@ -605,10 +604,6 @@ static inline void pwmchip_sysfs_export(struct pwm_chip *chip)
|
|||
static inline void pwmchip_sysfs_unexport(struct pwm_chip *chip)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void pwmchip_sysfs_unexport_children(struct pwm_chip *chip)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_PWM_SYSFS */
|
||||
|
||||
#endif /* __LINUX_PWM_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue