MIPS: OCTEON: octeon-usb: use bitfields for control register
Code needs to compile for all platforms in order to move it to drivers/usb/dwc3. Use Linux standard bitfield access macros to manipulate control register. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Ladislav Michl
Thomas Bogendoerfer
parent
c7b6a1eb2f
commit
ce942c0f69
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@ -8,16 +8,117 @@
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* for more details.
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*/
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#include <linux/module.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_platform.h>
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#include <asm/octeon/octeon.h>
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/*
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* USB Control Register
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*/
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#define USBDRD_UCTL_CTL 0x00
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/* BIST fast-clear mode select. A BIST run with this bit set
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* clears all entries in USBH RAMs to 0x0.
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*/
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# define USBDRD_UCTL_CTL_CLEAR_BIST BIT(63)
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/* 1 = Start BIST and cleared by hardware */
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# define USBDRD_UCTL_CTL_START_BIST BIT(62)
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/* Reference clock select for SuperSpeed and HighSpeed PLLs:
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* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
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* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
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* 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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*/
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# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK(61, 60)
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/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
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# define USBDRD_UCTL_CTL_SSC_EN BIT(59)
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/* Spread-spectrum clock modulation range:
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* 0x0 = -4980 ppm downspread
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* 0x1 = -4492 ppm downspread
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* 0x2 = -4003 ppm downspread
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* 0x3 - 0x7 = Reserved
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*/
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# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK(58, 56)
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/* Enable non-standard oscillator frequencies:
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* [55:53] = modules -1
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* [52:47] = 2's complement push amount, 0 = Feature disabled
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*/
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# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK(55, 47)
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/* Reference clock multiplier for non-standard frequencies:
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* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* Other Values = Reserved
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*/
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# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK(46, 40)
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/* Enable reference clock to prescaler for SuperSpeed functionality.
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* Should always be set to "1"
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*/
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# define USBDRD_UCTL_CTL_REF_SSP_EN BIT(39)
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/* Divide the reference clock by 2 before entering the
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* REF_CLK_FSEL divider:
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* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
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* If REF_CLK_SEL = 0x2 or 0x3, then:
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* 0x1 = DLMC_REF_CLK* is 125MHz
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* 0x0 = DLMC_REF_CLK* is another supported frequency
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*/
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# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT(38)
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/* Select reference clock freqnuency for both PLL blocks:
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* 0x27 = REF_CLK_SEL is 0x0 or 0x1
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* 0x07 = REF_CLK_SEL is 0x2 or 0x3
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*/
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# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK(37, 32)
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/* Controller clock enable. */
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# define USBDRD_UCTL_CTL_H_CLK_EN BIT(30)
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/* Select bypass input to controller clock divider:
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* 0x0 = Use divided coprocessor clock from H_CLKDIV
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* 0x1 = Use clock from GPIO pins
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*/
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# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT(29)
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/* Reset controller clock divider. */
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# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT(28)
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/* Clock divider select:
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* 0x0 = divide by 1
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* 0x1 = divide by 2
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* 0x2 = divide by 4
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* 0x3 = divide by 6
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* 0x4 = divide by 8
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* 0x5 = divide by 16
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* 0x6 = divide by 24
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* 0x7 = divide by 32
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*/
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# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK(26, 24)
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/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT(21)
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/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT(20)
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/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT(18)
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/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT(16)
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/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_SS_POWER_EN BIT(14)
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/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_HS_POWER_EN BIT(12)
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/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
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# define USBDRD_UCTL_CTL_CSCLK_EN BIT(4)
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/* Controller mode: 0x0 = Host, 0x1 = Device */
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# define USBDRD_UCTL_CTL_DRD_MODE BIT(3)
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/* PHY reset */
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# define USBDRD_UCTL_CTL_UPHY_RST BIT(2)
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/* Software reset UAHC */
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# define USBDRD_UCTL_CTL_UAHC_RST BIT(1)
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/* Software resets UCTL */
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# define USBDRD_UCTL_CTL_UCTL_RST BIT(0)
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#define USBDRD_UCTL_BIST_STATUS 0x08
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#define USBDRD_UCTL_SPARE0 0x10
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#define USBDRD_UCTL_INTSTAT 0x30
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@ -30,123 +131,6 @@
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#define USBDRD_UCTL_ECC 0xf0
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#define USBDRD_UCTL_SPARE1 0xf8
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/* USB Control Register */
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union cvm_usbdrd_uctl_ctl {
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uint64_t u64;
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struct cvm_usbdrd_uctl_ctl_s {
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/* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
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__BITFIELD_FIELD(uint64_t clear_bist:1,
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/* 1 = Start BIST and cleared by hardware */
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__BITFIELD_FIELD(uint64_t start_bist:1,
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/* Reference clock select for SuperSpeed and HighSpeed PLLs:
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* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
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* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
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* 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
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* HighSpeed PLL uses PLL_REF_CLK for reference clck
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*/
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__BITFIELD_FIELD(uint64_t ref_clk_sel:2,
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/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
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__BITFIELD_FIELD(uint64_t ssc_en:1,
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/* Spread-spectrum clock modulation range:
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* 0x0 = -4980 ppm downspread
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* 0x1 = -4492 ppm downspread
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* 0x2 = -4003 ppm downspread
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* 0x3 - 0x7 = Reserved
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*/
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__BITFIELD_FIELD(uint64_t ssc_range:3,
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/* Enable non-standard oscillator frequencies:
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* [55:53] = modules -1
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* [52:47] = 2's complement push amount, 0 = Feature disabled
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*/
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__BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
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/* Reference clock multiplier for non-standard frequencies:
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* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
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* Other Values = Reserved
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*/
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__BITFIELD_FIELD(uint64_t mpll_multiplier:7,
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/* Enable reference clock to prescaler for SuperSpeed functionality.
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* Should always be set to "1"
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*/
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__BITFIELD_FIELD(uint64_t ref_ssp_en:1,
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/* Divide the reference clock by 2 before entering the
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* REF_CLK_FSEL divider:
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* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
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* If REF_CLK_SEL = 0x2 or 0x3, then:
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* 0x1 = DLMC_REF_CLK* is 125MHz
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* 0x0 = DLMC_REF_CLK* is another supported frequency
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*/
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__BITFIELD_FIELD(uint64_t ref_clk_div2:1,
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/* Select reference clock freqnuency for both PLL blocks:
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* 0x27 = REF_CLK_SEL is 0x0 or 0x1
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* 0x07 = REF_CLK_SEL is 0x2 or 0x3
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*/
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__BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_31_31:1,
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/* Controller clock enable. */
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__BITFIELD_FIELD(uint64_t h_clk_en:1,
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/* Select bypass input to controller clock divider:
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* 0x0 = Use divided coprocessor clock from H_CLKDIV
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* 0x1 = Use clock from GPIO pins
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*/
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__BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
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/* Reset controller clock divider. */
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__BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_27_27:1,
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/* Clock divider select:
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* 0x0 = divide by 1
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* 0x1 = divide by 2
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* 0x2 = divide by 4
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* 0x3 = divide by 6
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* 0x4 = divide by 8
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* 0x5 = divide by 16
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* 0x6 = divide by 24
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* 0x7 = divide by 32
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*/
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__BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_22_23:2,
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/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
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/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_19_19:1,
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/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t usb3_port_disable:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_17_17:1,
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/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t usb2_port_disable:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_15_15:1,
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/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t ss_power_en:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_13_13:1,
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/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t hs_power_en:1,
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/* Reserved */
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__BITFIELD_FIELD(uint64_t reserved_5_11:7,
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/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
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__BITFIELD_FIELD(uint64_t csclk_en:1,
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/* Controller mode: 0x0 = Host, 0x1 = Device */
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__BITFIELD_FIELD(uint64_t drd_mode:1,
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/* PHY reset */
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__BITFIELD_FIELD(uint64_t uphy_rst:1,
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/* Software reset UAHC */
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__BITFIELD_FIELD(uint64_t uahc_rst:1,
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/* Software resets UCTL */
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__BITFIELD_FIELD(uint64_t uctl_rst:1,
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;)))))))))))))))))))))))))))))))))
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} s;
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};
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/* UAHC Configuration Register */
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union cvm_usbdrd_uctl_host_cfg {
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uint64_t u64;
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@ -297,14 +281,10 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
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static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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{
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union cvm_usbdrd_uctl_ctl uctl_ctl;
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int ref_clk_sel = 2;
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u64 div;
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int i, mpll_mul, ref_clk_fsel, ref_clk_sel = 2;
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u32 clock_rate;
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int mpll_mul;
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int i;
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u64 h_clk_rate;
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u64 uctl_ctl_reg = base;
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u64 div, h_clk_rate, val;
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u64 uctl_ctl_reg = base + USBDRD_UCTL_CTL;
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if (dev->of_node) {
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const char *ss_clock_type;
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@ -368,16 +348,16 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
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/* Step 3: Assert all resets. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.uphy_rst = 1;
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uctl_ctl.s.uahc_rst = 1;
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uctl_ctl.s.uctl_rst = 1;
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cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
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val = cvmx_read_csr(uctl_ctl_reg);
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val |= USBDRD_UCTL_CTL_UPHY_RST |
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USBDRD_UCTL_CTL_UAHC_RST |
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USBDRD_UCTL_CTL_UCTL_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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/* Step 4a: Reset the clock dividers. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.h_clkdiv_rst = 1;
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cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
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val = cvmx_read_csr(uctl_ctl_reg);
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val |= USBDRD_UCTL_CTL_H_CLKDIV_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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/* Step 4b: Select controller clock frequency. */
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for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
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@ -386,26 +366,29 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
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break;
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}
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.h_clkdiv_sel = div;
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uctl_ctl.s.h_clk_en = 1;
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cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {
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val = cvmx_read_csr(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);
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val |= USBDRD_UCTL_CTL_H_CLK_EN;
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cvmx_write_csr(uctl_ctl_reg, val);
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val = cvmx_read_csr(uctl_ctl_reg);
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if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) ||
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(!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) {
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dev_err(dev, "dwc3 controller clock init failure.\n");
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return -EINVAL;
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}
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/* Step 4c: Deassert the controller clock divider reset. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.h_clkdiv_rst = 0;
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cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
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val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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/* Step 5a: Reference clock configuration. */
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uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
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uctl_ctl.s.ref_clk_sel = ref_clk_sel;
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uctl_ctl.s.ref_clk_fsel = 0x07;
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uctl_ctl.s.ref_clk_div2 = 0;
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val = cvmx_read_csr(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2;
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val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
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ref_clk_fsel = 0x07;
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switch (clock_rate) {
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default:
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dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n",
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@ -414,7 +397,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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case 100000000:
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mpll_mul = 0x19;
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if (ref_clk_sel < 2)
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uctl_ctl.s.ref_clk_fsel = 0x27;
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ref_clk_fsel = 0x27;
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break;
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case 50000000:
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mpll_mul = 0x32;
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@ -423,28 +406,32 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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mpll_mul = 0x28;
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break;
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}
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uctl_ctl.s.mpll_multiplier = mpll_mul;
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val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel);
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val &= ~USBDRD_UCTL_CTL_MPLL_MULTIPLIER;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_MPLL_MULTIPLIER, mpll_mul);
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/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
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uctl_ctl.s.ssc_en = 1;
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val |= USBDRD_UCTL_CTL_SSC_EN;
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/* Step 5c: Enable SuperSpeed. */
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uctl_ctl.s.ref_ssp_en = 1;
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val |= USBDRD_UCTL_CTL_REF_SSP_EN;
|
||||
|
||||
/* Step 5d: Configure PHYs. SKIP */
|
||||
|
||||
/* Step 6a & 6b: Power up PHYs. */
|
||||
uctl_ctl.s.hs_power_en = 1;
|
||||
uctl_ctl.s.ss_power_en = 1;
|
||||
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
||||
val |= USBDRD_UCTL_CTL_HS_POWER_EN;
|
||||
val |= USBDRD_UCTL_CTL_SS_POWER_EN;
|
||||
cvmx_write_csr(uctl_ctl_reg, val);
|
||||
|
||||
/* Step 7: Wait 10 controller-clock cycles to take effect. */
|
||||
udelay(10);
|
||||
|
||||
/* Step 8a: Deassert UCTL reset signal. */
|
||||
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
|
||||
uctl_ctl.s.uctl_rst = 0;
|
||||
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
||||
val = cvmx_read_csr(uctl_ctl_reg);
|
||||
val &= ~USBDRD_UCTL_CTL_UCTL_RST;
|
||||
cvmx_write_csr(uctl_ctl_reg, val);
|
||||
|
||||
/* Step 8b: Wait 10 controller-clock cycles. */
|
||||
udelay(10);
|
||||
|
|
@ -454,22 +441,22 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
|
|||
return -EINVAL;
|
||||
|
||||
/* Step 8d: Deassert UAHC reset signal. */
|
||||
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
|
||||
uctl_ctl.s.uahc_rst = 0;
|
||||
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
||||
val = cvmx_read_csr(uctl_ctl_reg);
|
||||
val &= ~USBDRD_UCTL_CTL_UAHC_RST;
|
||||
cvmx_write_csr(uctl_ctl_reg, val);
|
||||
|
||||
/* Step 8e: Wait 10 controller-clock cycles. */
|
||||
udelay(10);
|
||||
|
||||
/* Step 9: Enable conditional coprocessor clock of UCTL. */
|
||||
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
|
||||
uctl_ctl.s.csclk_en = 1;
|
||||
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
||||
val = cvmx_read_csr(uctl_ctl_reg);
|
||||
val |= USBDRD_UCTL_CTL_CSCLK_EN;
|
||||
cvmx_write_csr(uctl_ctl_reg, val);
|
||||
|
||||
/*Step 10: Set for host mode only. */
|
||||
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
|
||||
uctl_ctl.s.drd_mode = 0;
|
||||
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
|
||||
val = cvmx_read_csr(uctl_ctl_reg);
|
||||
val &= ~USBDRD_UCTL_CTL_DRD_MODE;
|
||||
cvmx_write_csr(uctl_ctl_reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -491,11 +478,12 @@ static void __init dwc3_octeon_set_endian_mode(u64 base)
|
|||
|
||||
static void __init dwc3_octeon_phy_reset(u64 base)
|
||||
{
|
||||
union cvm_usbdrd_uctl_ctl uctl_ctl;
|
||||
u64 val;
|
||||
u64 uctl_ctl_reg = base + USBDRD_UCTL_CTL;
|
||||
|
||||
uctl_ctl.u64 = cvmx_read_csr(base + USBDRD_UCTL_CTL);
|
||||
uctl_ctl.s.uphy_rst = 0;
|
||||
cvmx_write_csr(base + USBDRD_UCTL_CTL, uctl_ctl.u64);
|
||||
val = cvmx_read_csr(uctl_ctl_reg);
|
||||
val &= ~USBDRD_UCTL_CTL_UPHY_RST;
|
||||
cvmx_write_csr(uctl_ctl_reg, val);
|
||||
}
|
||||
|
||||
static int __init dwc3_octeon_device_init(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue