drm/amd/display: Screen corruption on dual displays (DP+USB-C)
[why] Current pipe merge and split logic only supports cases where new dc_state is allocated and relies on dc->current_state to gather information from previous dc_state. Calls to validate_bandwidth on UPDATE_TYPE_MED would cause an issue because there is no new dc_state allocated, and data in dc->current_state would be overwritten during pipe merge. [how] Only allow validate_bandwidth when new dc_state space is created. Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2636,7 +2636,7 @@ void dc_commit_updates_for_stream(struct dc *dc,
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copy_stream_update_to_stream(dc, context, stream, stream_update);
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copy_stream_update_to_stream(dc, context, stream, stream_update);
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if (update_type > UPDATE_TYPE_FAST) {
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if (update_type >= UPDATE_TYPE_FULL) {
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if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
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if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
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DC_ERROR("Mode validation failed for stream update!\n");
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DC_ERROR("Mode validation failed for stream update!\n");
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dc_release_state(context);
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dc_release_state(context);
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@ -3209,6 +3209,9 @@ static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
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context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
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context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive =
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dc->debug.enable_dram_clock_change_one_display_vactive;
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dc->debug.enable_dram_clock_change_one_display_vactive;
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/*Unsafe due to current pipe merge and split logic*/
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ASSERT(context != dc->current_state);
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if (fast_validate) {
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if (fast_validate) {
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return dcn20_validate_bandwidth_internal(dc, context, true);
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return dcn20_validate_bandwidth_internal(dc, context, true);
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}
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}
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@ -1184,6 +1184,9 @@ bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
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BW_VAL_TRACE_COUNT();
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BW_VAL_TRACE_COUNT();
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/*Unsafe due to current pipe merge and split logic*/
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ASSERT(context != dc->current_state);
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out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
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out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
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if (pipe_cnt == 0)
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if (pipe_cnt == 0)
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