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drm/i915: s/intel_gen4_compute_page_offset/intel_compute_tile_offset/ 

Since intel_gen4_compute_page_offset() can now handle tiling formats
all the way down to gen2, rename it to intel_compute_tile_offset().
Not that we actually use it on gen2/3 since there's no DSPSURF etc.
registers which would take a page aligned address.

v2: s/page/tile/ (Daniel)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1452625717-9713-7-git-send-email-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä 2016-01-12 21:08:36 +02:00
parent d843310d14
commit ce1e5c140c
3 changed files with 30 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/i915/intel_display.c
View File

@ -2457,7 +2457,7 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
* is assumed to be a power-of-two. */
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
uint64_t fb_modifier,
unsigned int cpp,
@ -2784,7 +2784,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
if (INTEL_INFO(dev)->gen >= 4) {
intel_crtc->dspaddr_offset =
intel_gen4_compute_page_offset(dev_priv, &x, &y,
intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);
@ -2892,7 +2892,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
linear_offset = y * fb->pitches[0] + x * pixel_size;
intel_crtc->dspaddr_offset =
intel_gen4_compute_page_offset(dev_priv, &x, &y,
intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);

2
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1195,7 +1195,7 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
uint64_t fb_modifier,
unsigned int cpp,

6
drivers/gpu/drm/i915/intel_sprite.c
View File

@ -423,7 +423,7 @@ vlv_update_plane(struct drm_plane *dplane,
crtc_h--;
linear_offset = y * fb->pitches[0] + x * pixel_size;
sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);
@ -557,7 +557,7 @@ ivb_update_plane(struct drm_plane *plane,
sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * pixel_size;
sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);
@ -696,7 +696,7 @@ ilk_update_plane(struct drm_plane *plane,
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
linear_offset = y * fb->pitches[0] + x * pixel_size;
dvssurf_offset = intel_gen4_compute_page_offset(dev_priv, &x, &y,
dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
fb->modifier[0],
pixel_size,
fb->pitches[0]);