drm/amdgpu: remove the unnecessary parameter adev for amdgpu_fence_wait_any()
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -447,8 +447,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
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unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
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unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
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signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
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signed long amdgpu_fence_wait_any(struct fence **array,
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struct fence **array,
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uint32_t count,
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uint32_t count,
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bool intr,
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bool intr,
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signed long t);
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signed long t);
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@ -857,16 +857,12 @@ static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
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static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
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static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
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signed long t)
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signed long t)
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{
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{
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struct amdgpu_fence *fence = to_amdgpu_fence(f);
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return amdgpu_fence_wait_any(&f, 1, intr, t);
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struct amdgpu_device *adev = fence->ring->adev;
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return amdgpu_fence_wait_any(adev, &f, 1, intr, t);
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}
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}
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/**
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/**
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* Wait the fence array with timeout
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* Wait the fence array with timeout
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*
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*
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* @adev: amdgpu device
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* @array: the fence array with amdgpu fence pointer
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* @array: the fence array with amdgpu fence pointer
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* @count: the number of the fence array
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* @count: the number of the fence array
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* @intr: when sleep, set the current task interruptable or not
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* @intr: when sleep, set the current task interruptable or not
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@ -874,8 +870,7 @@ static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
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*
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*
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* It will return when any fence is signaled or timeout.
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* It will return when any fence is signaled or timeout.
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*/
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*/
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signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
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signed long amdgpu_fence_wait_any(struct fence **array, uint32_t count,
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struct fence **array, uint32_t count,
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bool intr, signed long t)
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bool intr, signed long t)
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{
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{
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struct amdgpu_wait_cb *cb;
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struct amdgpu_wait_cb *cb;
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@ -372,7 +372,7 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev,
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} while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
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} while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
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spin_unlock(&sa_manager->wq.lock);
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spin_unlock(&sa_manager->wq.lock);
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t = amdgpu_fence_wait_any(adev, fences, AMDGPU_MAX_RINGS,
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t = amdgpu_fence_wait_any(fences, AMDGPU_MAX_RINGS,
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false, MAX_SCHEDULE_TIMEOUT);
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false, MAX_SCHEDULE_TIMEOUT);
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r = (t > 0) ? 0 : t;
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r = (t > 0) ? 0 : t;
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spin_lock(&sa_manager->wq.lock);
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spin_lock(&sa_manager->wq.lock);
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