arm64: tegra: Changes for v4.16-rc1
This set of patches enables a bunch of new features on Jetson TX2 that were finally unblocked by the GPIO driver getting merged for v4.15. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlo6tuMTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zodskD/wLlXn2w48dUcTJDqwQr5I4FsLKe99u si2Ci4MW3M/62apNGpc7HaKE5H7XWYuzeL282IJEKwPpnzg3YGb+9cvgi9fyjgOz G+Faze57wMWzfFvEQBoNXtOjA/6W9jeurxm/41naTVl9XtKYxIXUECwKxdZboT2t 9lfJIuAJIWKh8MCpWf9LzNJPW9lld5rbxk/M7htczsCPdmPNdSZwJQMh9lJmw2Mc fBOp4NbY4gU3Tcaua9NWaEMUC5Zf07FgEaQldH1gsRAOlA5ZlraHBjjUcQq/kOTf ApRcnIUpR4BdC5GPKn49ahrPrPwfKNdfLaeynd1WL9+ELnFSzBYotLVmWIGExxDc F3cIzkEmAX5xzjLs/eCeX3rlW1jvBcx0+nxZ2TkuBnKegG4tL0cma2W1k6pcU4xj s3WDmdGcr5U1a1/a/CCSn7nV7SKgJVr5knuwxiZKqtQlzyjJI5VidfhT4yJ0pnsk t2Eird2eWH9O8CjvpEya4gc6QKUdj6/VoykutJUfw0aApIIY2ZGWYQ6l9tf9pE6O RYEOhX9oS2XL5NUGiu5CE3XdjIaMcZ53qkqH0U1wd1yfc3siWKilZ/2OPEaDG3tH YNQZkoLQ6P5rOz+YNhSI9VCYXIkJ/A/XbSg+NAvnxfLxVcPZ0XcIZYS8SNbORMUf EsrMYd4QiIjtyA== =7QxU -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.16-arm64-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt Pull "arm64: tegra: Changes for v4.16-rc1" from Thierry Reding: This set of patches enables a bunch of new features on Jetson TX2 that were finally unblocked by the GPIO driver getting merged for v4.15. * tag 'tegra-for-4.16-arm64-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Use sor1_out clock arm64: tegra: Fix SD write-protect polarity on Jetson TX2 arm64: tegra: Add CPU and PSCI nodes for NVIDIA Tegra210 platforms arm64: tegra: Enable HDMI on Jetson TX2 arm64: tegra: Mark I2C4 as DDC on P3310 arm64: tegra: Add display nodes on Tegra186 arm64: tegra: Add SMMU node for Tegra186 arm64: tegra: Enable memory controller on P3310 arm64: tegra: Add memory controller on Tegra186 arm64: tegra: Add FUSE block on Tegra186 arm64: tegra: Add MISC registers on Tegra186
This commit is contained in:
Arnd Bergmann
commit
cd9787e829
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@ -74,6 +74,43 @@
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};
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};
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host1x@13e00000 {
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status = "okay";
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dpaux@15040000 {
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status = "okay";
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};
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display-hub@15200000 {
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status = "okay";
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};
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dsi@15300000 {
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status = "disabled";
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};
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sor@15540000 {
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status = "disabled";
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nvidia,dpaux = <&dpaux1>;
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};
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sor@15580000 {
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status = "okay";
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avdd-io-supply = <&vdd_hdmi_1v05>;
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vdd-pll-supply = <&vdd_1v8_ap>;
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hdmi-supply = <&vdd_hdmi>;
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nvidia,ddc-i2c-bus = <&ddc>;
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nvidia,hpd-gpio = <&gpio TEGRA_MAIN_GPIO(P, 1) GPIO_ACTIVE_LOW>;
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};
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dpaux@155c0000 {
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status = "okay";
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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@ -120,5 +157,19 @@
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vin-supply = <&vdd_3v3_sys>;
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};
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vdd_hdmi: regulator@101 {
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compatible = "regulator-fixed";
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reg = <101>;
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regulator-name = "VDD_HDMI_5V0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&exp1 14 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <&vdd_5v0_sys>;
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};
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};
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};
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@ -51,6 +51,10 @@
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};
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};
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memory-controller@2c00000 {
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status = "okay";
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};
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serial@3100000 {
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status = "okay";
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};
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@ -73,7 +77,7 @@
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status = "okay";
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};
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i2c@3190000 {
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ddc: i2c@3190000 {
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status = "okay";
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};
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@ -88,7 +92,7 @@
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/* SDMMC1 (SD/MMC) */
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sdhci@3400000 {
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cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
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vqmmc-supply = <&vddio_sdmmc1>;
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};
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@ -317,7 +321,7 @@
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regulator-max-microvolt = <2800000>;
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};
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avdd_1v05: ldo7 {
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vdd_hdmi_1v05: ldo7 {
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regulator-name = "VDD_HDMI_1V05";
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1050000>;
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@ -3,6 +3,7 @@
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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#include <dt-bindings/power/tegra186-powergate.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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@ -13,6 +14,12 @@
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#address-cells = <2>;
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#size-cells = <2>;
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misc@100000 {
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compatible = "nvidia,tegra186-misc";
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reg = <0x0 0x00100000 0x0 0xf000>,
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<0x0 0x0010f000 0x0 0x1000>;
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};
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gpio: gpio@2200000 {
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compatible = "nvidia,tegra186-gpio";
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reg-names = "security", "gpio";
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@ -61,6 +68,12 @@
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snps,rxpbl = <8>;
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};
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memory-controller@2c00000 {
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compatible = "nvidia,tegra186-mc";
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reg = <0x0 0x02c00000 0x0 0xb0000>;
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status = "disabled";
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03100000 0x0 0x40>;
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@ -259,6 +272,13 @@
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status = "disabled";
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};
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fuse@3820000 {
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compatible = "nvidia,tegra186-efuse";
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reg = <0x0 0x03820000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_FUSE>;
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clock-names = "fuse";
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};
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gic: interrupt-controller@3881000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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@ -437,6 +457,79 @@
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};
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};
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smmu: iommu@12000000 {
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compatible = "arm,mmu-500";
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reg = <0 0x12000000 0 0x800000>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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stream-match-mask = <0x7f80>;
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#global-interrupts = <1>;
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#iommu-cells = <1>;
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};
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host1x@13e00000 {
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compatible = "nvidia,tegra186-host1x", "simple-bus";
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reg = <0x0 0x13e00000 0x0 0x10000>,
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@ -453,6 +546,129 @@
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#size-cells = <1>;
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ranges = <0x15000000 0x0 0x15000000 0x01000000>;
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iommus = <&smmu TEGRA186_SID_HOST1X>;
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dpaux1: dpaux@15040000 {
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compatible = "nvidia,tegra186-dpaux";
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reg = <0x15040000 0x10000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
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<&bpmp TEGRA186_CLK_PLLDP>;
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clock-names = "dpaux", "parent";
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resets = <&bpmp TEGRA186_RESET_DPAUX1>;
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reset-names = "dpaux";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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state_dpaux1_aux: pinmux-aux {
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groups = "dpaux-io";
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function = "aux";
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};
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state_dpaux1_i2c: pinmux-i2c {
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groups = "dpaux-io";
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function = "i2c";
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};
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state_dpaux1_off: pinmux-off {
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groups = "dpaux-io";
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function = "off";
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};
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i2c-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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display-hub@15200000 {
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compatible = "nvidia,tegra186-display", "simple-bus";
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resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
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<&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
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reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
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"wgrp3", "wgrp4", "wgrp5";
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clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
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<&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
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<&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
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clock-names = "disp", "dsc", "hub";
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status = "disabled";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x15200000 0x15200000 0x40000>;
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display@15200000 {
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compatible = "nvidia,tegra186-dc";
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reg = <0x15200000 0x10000>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
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clock-names = "dc";
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resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
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reset-names = "dc";
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||||
|
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
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iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
|
||||
|
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nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
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nvidia,head = <0>;
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||||
};
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||||
|
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display@15210000 {
|
||||
compatible = "nvidia,tegra186-dc";
|
||||
reg = <0x15210000 0x10000>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
|
||||
clock-names = "dc";
|
||||
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
|
||||
reset-names = "dc";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
|
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iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
|
||||
|
||||
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
|
||||
nvidia,head = <1>;
|
||||
};
|
||||
|
||||
display@15220000 {
|
||||
compatible = "nvidia,tegra186-dc";
|
||||
reg = <0x15220000 0x10000>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
|
||||
clock-names = "dc";
|
||||
resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
|
||||
reset-names = "dc";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
|
||||
iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
|
||||
|
||||
nvidia,outputs = <&sor0 &sor1>;
|
||||
nvidia,head = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
dsia: dsi@15300000 {
|
||||
compatible = "nvidia,tegra186-dsi";
|
||||
reg = <0x15300000 0x10000>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSI>,
|
||||
<&bpmp TEGRA186_CLK_DSIA_LP>,
|
||||
<&bpmp TEGRA186_CLK_PLLD>;
|
||||
clock-names = "dsi", "lp", "parent";
|
||||
resets = <&bpmp TEGRA186_RESET_DSI>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
||||
};
|
||||
|
||||
vic@15340000 {
|
||||
compatible = "nvidia,tegra186-vic";
|
||||
|
|
@ -465,6 +681,141 @@
|
|||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
|
||||
};
|
||||
|
||||
dsib: dsi@15400000 {
|
||||
compatible = "nvidia,tegra186-dsi";
|
||||
reg = <0x15400000 0x10000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSIB>,
|
||||
<&bpmp TEGRA186_CLK_DSIB_LP>,
|
||||
<&bpmp TEGRA186_CLK_PLLD>;
|
||||
clock-names = "dsi", "lp", "parent";
|
||||
resets = <&bpmp TEGRA186_RESET_DSIB>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
||||
};
|
||||
|
||||
sor0: sor@15540000 {
|
||||
compatible = "nvidia,tegra186-sor";
|
||||
reg = <0x15540000 0x10000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SOR0>,
|
||||
<&bpmp TEGRA186_CLK_SOR0_OUT>,
|
||||
<&bpmp TEGRA186_CLK_PLLD2>,
|
||||
<&bpmp TEGRA186_CLK_PLLDP>,
|
||||
<&bpmp TEGRA186_CLK_SOR_SAFE>,
|
||||
<&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
|
||||
clock-names = "sor", "out", "parent", "dp", "safe",
|
||||
"pad";
|
||||
resets = <&bpmp TEGRA186_RESET_SOR0>;
|
||||
reset-names = "sor";
|
||||
pinctrl-0 = <&state_dpaux_aux>;
|
||||
pinctrl-1 = <&state_dpaux_i2c>;
|
||||
pinctrl-2 = <&state_dpaux_off>;
|
||||
pinctrl-names = "aux", "i2c", "off";
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
||||
nvidia,interface = <0>;
|
||||
};
|
||||
|
||||
sor1: sor@15580000 {
|
||||
compatible = "nvidia,tegra186-sor1";
|
||||
reg = <0x15580000 0x10000>;
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SOR1>,
|
||||
<&bpmp TEGRA186_CLK_SOR1_OUT>,
|
||||
<&bpmp TEGRA186_CLK_PLLD3>,
|
||||
<&bpmp TEGRA186_CLK_PLLDP>,
|
||||
<&bpmp TEGRA186_CLK_SOR_SAFE>,
|
||||
<&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
|
||||
clock-names = "sor", "out", "parent", "dp", "safe",
|
||||
"pad";
|
||||
resets = <&bpmp TEGRA186_RESET_SOR1>;
|
||||
reset-names = "sor";
|
||||
pinctrl-0 = <&state_dpaux1_aux>;
|
||||
pinctrl-1 = <&state_dpaux1_i2c>;
|
||||
pinctrl-2 = <&state_dpaux1_off>;
|
||||
pinctrl-names = "aux", "i2c", "off";
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
||||
nvidia,interface = <1>;
|
||||
};
|
||||
|
||||
dpaux: dpaux@155c0000 {
|
||||
compatible = "nvidia,tegra186-dpaux";
|
||||
reg = <0x155c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DPAUX>,
|
||||
<&bpmp TEGRA186_CLK_PLLDP>;
|
||||
clock-names = "dpaux", "parent";
|
||||
resets = <&bpmp TEGRA186_RESET_DPAUX>;
|
||||
reset-names = "dpaux";
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
||||
|
||||
state_dpaux_aux: pinmux-aux {
|
||||
groups = "dpaux-io";
|
||||
function = "aux";
|
||||
};
|
||||
|
||||
state_dpaux_i2c: pinmux-i2c {
|
||||
groups = "dpaux-io";
|
||||
function = "i2c";
|
||||
};
|
||||
|
||||
state_dpaux_off: pinmux-off {
|
||||
groups = "dpaux-io";
|
||||
function = "off";
|
||||
};
|
||||
|
||||
i2c-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
padctl@15880000 {
|
||||
compatible = "nvidia,tegra186-dsi-padctl";
|
||||
reg = <0x15880000 0x10000>;
|
||||
resets = <&bpmp TEGRA186_RESET_DSI>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dsic: dsi@15900000 {
|
||||
compatible = "nvidia,tegra186-dsi";
|
||||
reg = <0x15900000 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSIC>,
|
||||
<&bpmp TEGRA186_CLK_DSIC_LP>,
|
||||
<&bpmp TEGRA186_CLK_PLLD>;
|
||||
clock-names = "dsi", "lp", "parent";
|
||||
resets = <&bpmp TEGRA186_RESET_DSIC>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
||||
};
|
||||
|
||||
dsid: dsi@15940000 {
|
||||
compatible = "nvidia,tegra186-dsi";
|
||||
reg = <0x15940000 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_DSID>,
|
||||
<&bpmp TEGRA186_CLK_DSID_LP>,
|
||||
<&bpmp TEGRA186_CLK_PLLD>;
|
||||
clock-names = "dsi", "lp", "parent";
|
||||
resets = <&bpmp TEGRA186_RESET_DSID>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
|
||||
};
|
||||
};
|
||||
|
||||
gpu@17000000 {
|
||||
|
|
|
|||
|
|
@ -297,6 +297,29 @@
|
|||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_gpu: regulator@100 {
|
||||
compatible = "pwm-regulator";
|
||||
|
|
|
|||
|
|
@ -52,4 +52,27 @@
|
|||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -266,11 +266,11 @@
|
|||
reg = <0x0 0x54580000 0x0 0x00040000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SOR1>,
|
||||
<&tegra_car TEGRA210_CLK_SOR1_SRC>,
|
||||
<&tegra_car TEGRA210_CLK_SOR1_OUT>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_DP>,
|
||||
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
|
||||
clock-names = "sor", "source", "parent", "dp", "safe";
|
||||
clock-names = "sor", "out", "parent", "dp", "safe";
|
||||
resets = <&tegra_car 183>;
|
||||
reset-names = "sor";
|
||||
pinctrl-0 = <&state_dpaux1_aux>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue