drm/amdgpu: add partition schedule for GC(9, 4, 3)

Implement partition schedule for GC(9, 4, 3).

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu 2022-08-15 17:00:54 -04:00 committed by Alex Deucher
parent c30e326e48
commit cd7d8400aa
1 changed files with 41 additions and 0 deletions

View File

@ -166,6 +166,46 @@ static int aqua_vanjaram_update_partition_sched_list(struct amdgpu_device *adev)
return aqua_vanjaram_xcp_sched_list_update(adev);
}
int aqua_vanjaram_select_scheds(
struct amdgpu_device *adev,
u32 hw_ip,
u32 hw_prio,
struct amdgpu_fpriv *fpriv,
unsigned int *num_scheds,
struct drm_gpu_scheduler ***scheds)
{
u32 sel_xcp_id;
int i;
if (fpriv->xcp_id == ~0) {
u32 least_ref_cnt = ~0;
fpriv->xcp_id = 0;
for (i = 0; i < adev->xcp_mgr->num_xcps; i++) {
u32 total_ref_cnt;
total_ref_cnt = atomic_read(&adev->xcp_mgr->xcp[i].ref_cnt);
if (total_ref_cnt < least_ref_cnt) {
fpriv->xcp_id = i;
least_ref_cnt = total_ref_cnt;
}
}
}
sel_xcp_id = fpriv->xcp_id;
if (adev->xcp_mgr->xcp[sel_xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds) {
*num_scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds;
*scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].sched;
atomic_inc(&adev->xcp_mgr->xcp[sel_xcp_id].ref_cnt);
DRM_DEBUG("Selected partition #%d", sel_xcp_id);
} else {
DRM_ERROR("Failed to schedule partition #%d.", sel_xcp_id);
return -ENOENT;
}
return 0;
}
static int8_t aqua_vanjaram_logical_to_dev_inst(struct amdgpu_device *adev,
enum amd_hw_ip_block_type block,
int8_t inst)
@ -548,6 +588,7 @@ struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = {
.query_partition_mode = &aqua_vanjaram_query_partition_mode,
.get_ip_details = &aqua_vanjaram_get_xcp_ip_details,
.get_xcp_mem_id = &aqua_vanjaram_get_xcp_mem_id,
.select_scheds = &aqua_vanjaram_select_scheds,
.update_partition_sched_list = &aqua_vanjaram_update_partition_sched_list
};