drm/amdgpu: add partition schedule for GC(9, 4, 3)
Implement partition schedule for GC(9, 4, 3). Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -166,6 +166,46 @@ static int aqua_vanjaram_update_partition_sched_list(struct amdgpu_device *adev)
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return aqua_vanjaram_xcp_sched_list_update(adev);
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}
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int aqua_vanjaram_select_scheds(
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struct amdgpu_device *adev,
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u32 hw_ip,
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u32 hw_prio,
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struct amdgpu_fpriv *fpriv,
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unsigned int *num_scheds,
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struct drm_gpu_scheduler ***scheds)
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{
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u32 sel_xcp_id;
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int i;
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if (fpriv->xcp_id == ~0) {
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u32 least_ref_cnt = ~0;
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fpriv->xcp_id = 0;
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for (i = 0; i < adev->xcp_mgr->num_xcps; i++) {
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u32 total_ref_cnt;
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total_ref_cnt = atomic_read(&adev->xcp_mgr->xcp[i].ref_cnt);
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if (total_ref_cnt < least_ref_cnt) {
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fpriv->xcp_id = i;
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least_ref_cnt = total_ref_cnt;
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}
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}
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}
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sel_xcp_id = fpriv->xcp_id;
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if (adev->xcp_mgr->xcp[sel_xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds) {
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*num_scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds;
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*scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].sched;
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atomic_inc(&adev->xcp_mgr->xcp[sel_xcp_id].ref_cnt);
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DRM_DEBUG("Selected partition #%d", sel_xcp_id);
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} else {
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DRM_ERROR("Failed to schedule partition #%d.", sel_xcp_id);
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return -ENOENT;
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}
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return 0;
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}
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static int8_t aqua_vanjaram_logical_to_dev_inst(struct amdgpu_device *adev,
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enum amd_hw_ip_block_type block,
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int8_t inst)
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@ -548,6 +588,7 @@ struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = {
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.query_partition_mode = &aqua_vanjaram_query_partition_mode,
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.get_ip_details = &aqua_vanjaram_get_xcp_ip_details,
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.get_xcp_mem_id = &aqua_vanjaram_get_xcp_mem_id,
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.select_scheds = &aqua_vanjaram_select_scheds,
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.update_partition_sched_list = &aqua_vanjaram_update_partition_sched_list
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};
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