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Staging/cxt1e1/comet.c:Modifying comment style and intentation 

This patch modifies the commenting style by placing comments above the
line of code commented upone.

Signed-off-by: Dulshani Gunawardhana <dulshani.gunawardhana89@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Dulshani Gunawardhana 2013-05-22 23:13:05 +05:30 committed by Greg Kroah-Hartman
parent 4a9fbb2788
commit cd1ccce165
1 changed files with 333 additions and 312 deletions
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645
drivers/staging/cxt1e1/comet.c
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@ -42,132 +42,126 @@ STATIC void WrtXmtWaveformTbl(ci_t * ci, comet_t * comet, u_int8_t table[COMET_N
void *TWV_table[12] = { void *TWV_table[12] = {
TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB, TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3, TWVShortHaul4, TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
TWVShortHaul5, TWVShortHaul4, TWVShortHaul5,
TWV_E1_75Ohm, /** PORT POINT - 75 Ohm not supported **/ /** PORT POINT - 75 Ohm not supported **/
TWV_E1_75Ohm,
TWV_E1_120Ohm TWV_E1_120Ohm
}; };
static int static int
lbo_tbl_lkup(int t1, int lbo) lbo_tbl_lkup(int t1, int lbo) {
{ /* error switches to default */
if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) /* error switches to if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
* default */
{
if (t1) if (t1)
lbo = CFG_LBO_LH0; /* default T1 waveform table */ /* default T1 waveform table */
lbo = CFG_LBO_LH0;
else else
lbo = CFG_LBO_E120; /* default E1 waveform table */ /* default E1 waveform table */
lbo = CFG_LBO_E120;
} }
return (lbo - 1); /* make index ZERO relative */ /* make index ZERO relative */
return (lbo - 1);
} }
void init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
void u_int8_t moreParams)
init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
u_int8_t moreParams)
{ {
u_int8_t isT1mode; u_int8_t isT1mode;
u_int8_t tix = CFG_LBO_LH0; /* T1 default */ /* T1 default */
u_int8_t tix = CFG_LBO_LH0;
isT1mode = IS_FRAME_ANY_T1 (port_mode); isT1mode = IS_FRAME_ANY_T1(port_mode);
/* T1 or E1 */ /* T1 or E1 */
if (isT1mode) if (isT1mode) {
{ /* Select T1 Mode & PIO output enabled */
pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0xa0); /* Select T1 Mode & PIO pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
* output enabled */ /* default T1 waveform table */
tix = lbo_tbl_lkup (isT1mode, CFG_LBO_LH0); /* default T1 waveform tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
* table */ } else {
} else /* Select E1 Mode & PIO output enabled */
{ pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81); /* Select E1 Mode & PIO /* default E1 waveform table */
* output enabled */ tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
tix = lbo_tbl_lkup (isT1mode, CFG_LBO_E120); /* default E1 waveform
* table */
} }
if (moreParams & CFG_LBO_MASK) if (moreParams & CFG_LBO_MASK)
tix = lbo_tbl_lkup (isT1mode, moreParams & CFG_LBO_MASK); /* dial-in requested /* dial-in requested waveform table */
* waveform table */ tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
/* Tx line Intfc cfg Set for analog & no special patterns */
/* Tx line Intfc cfg ** Set for analog & no special patterns */ /* Transmit Line Interface Config. */
pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00); /* Transmit Line pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
* Interface Config. */ /* master test Ignore Test settings for now */
/* making sure it's Default value */
/* master test ** Ignore Test settings for now */ pci_write_32((u_int32_t *) &comet->mtest, 0x00);
pci_write_32((u_int32_t *) &comet->mtest, 0x00); /* making sure it's /* Turn on Center (CENT) and everything else off */
* Default value */ /* RJAT cfg */
pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
/* Turn on Center (CENT) and everything else off */ /* Set Jitter Attenuation to recommend T1 values */
pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10); /* RJAT cfg */ if (isT1mode) {
/* Set Jitter Attenuation to recommend T1 values */ /* RJAT Divider N1 Control */
if (isT1mode) pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
{ /* RJAT Divider N2 Control */
pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F); /* RJAT Divider N1 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
* Control */ } else {
pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F); /* RJAT Divider N2 /* RJAT Divider N1 Control */
* Control */ pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
} else /* RJAT Divider N2 Control */
{ pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF); /* RJAT Divider N1
* Control */
pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF); /* RJAT Divider N2
* Control */
} }
/* Turn on Center (CENT) and everything else off */ /* Turn on Center (CENT) and everything else off */
pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10); /* TJAT Config. */ /* TJAT Config. */
pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
/* Do not bypass jitter attenuation and bypass elastic store */ /* Do not bypass jitter attenuation and bypass elastic store */
pci_write_32((u_int32_t *) &comet->rx_opt, 0x00); /* rx opts */ /* rx opts */
pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
/* TJAT ctrl & TJAT divider ctrl */ /* TJAT ctrl & TJAT divider ctrl */
/* Set Jitter Attenuation to recommended T1 values */ /* Set Jitter Attenuation to recommended T1 values */
if (isT1mode) if (isT1mode) {
{ /* TJAT Divider N1 Control */
pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F); /* TJAT Divider N1 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
* Control */ /* TJAT Divider N2 Control */
pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F); /* TJAT Divider N2 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
* Control */ } else {
} else /* TJAT Divider N1 Control */
{ pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF); /* TJAT Divider N1 /* TJAT Divider N2 Control */
* Control */ pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF); /* TJAT Divider N2
* Control */
} }
/* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */ /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
if (isT1mode)
{ /* Select 193-bit frame format */ /* Select 193-bit frame format */
if (isT1mode) {
pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00); pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00); pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
} else } else {
{ /* Select 256-bit frame format */ /* Select 256-bit frame format */
pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03); pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03); pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00); /* disable T1 data link /* disable T1 data link receive */
* receive */ pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00); /* disable T1 data link /* disable T1 data link transmit */
* transmit */ pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
} }
/* the following is a default value */ /* the following is a default value */
/* Enable 8 out of 10 validation */ /* Enable 8 out of 10 validation */
pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00); /* t1RBOC /* t1RBOC enable(BOC:BitOriented Code) */
* enable(BOC:BitOriented pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
* Code) */
if (isT1mode) if (isT1mode)
{ {
/* IBCD cfg: aka Inband Code Detection ** loopback code length set to */ /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04); /* 6 bit down, 5 bit up /* 6 bit down, 5 bit up (assert) */
* (assert) */ pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08); /* line loopback /* line loopback activate pattern */
* activate pattern */ pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24); /* deactivate code /* deactivate code pattern (i.e.001) */
* pattern (i.e.001) */ pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
} }
/* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */ /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */
/* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */ /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */
@ -176,94 +170,118 @@ init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
switch (port_mode) switch (port_mode)
{ {
case CFG_FRAME_SF: /* 1 - T1 B8ZS */ /* 1 - T1 B8ZS */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); case CFG_FRAME_SF:
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0); pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20); /* 5:B8ZS */
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
break;
case CFG_FRAME_ESF: /* 2 - T1 B8ZS */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20); /* Bit 5: T1 DataLink
* Enable */
pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* 4:ESF 5:ESFFA */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30); /* 4:ESF 5:B8ZS */
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */
break;
case CFG_FRAME_E1PLAIN: /* 3 - HDB3 */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
break;
case CFG_FRAME_E1CAS: /* 4 - HDB3 */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
break;
case CFG_FRAME_E1CRC: /* 5 - HDB3 */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
break;
case CFG_FRAME_E1CRC_CAS: /* 6 - HDB3 */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
break;
case CFG_FRAME_SF_AMI: /* 7 - T1 AMI */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
* Decoding */
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
break;
case CFG_FRAME_ESF_AMI: /* 8 - T1 AMI */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
* Decoding */
pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20); /* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* Bit 4:ESF 5:ESFFA */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10); /* 4:ESF */
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */
break;
case CFG_FRAME_E1PLAIN_AMI: /* 9 - AMI */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
* Decoding */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
break;
case CFG_FRAME_E1CAS_AMI: /* 10 - AMI */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
* Decoding */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
break;
case CFG_FRAME_E1CRC_AMI: /* 11 - AMI */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
* Decoding */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
break;
case CFG_FRAME_E1CRC_CAS_AMI: /* 12 - AMI */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
* Decoding */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0); pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0); /* 5:B8ZS */
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82); pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
break; pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
} /* end switch */ break;
/* 2 - T1 B8ZS */
case CFG_FRAME_ESF:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
/* Bit 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
/* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
/* 4:ESF 5:ESFFA */
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
/* 2:ESF */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
/* 4:ESF 5:B8ZS */
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
/* 4:ESF */
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
break;
/* 3 - HDB3 */
case CFG_FRAME_E1PLAIN:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
break;
/* 4 - HDB3 */
case CFG_FRAME_E1CAS:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
break;
/* 5 - HDB3 */
case CFG_FRAME_E1CRC:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
break;
/* 6 - HDB3 */
case CFG_FRAME_E1CRC_CAS:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
break;
/* 7 - T1 AMI */
case CFG_FRAME_SF_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
break;
/* 8 - T1 AMI */
case CFG_FRAME_ESF_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
/* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
/* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
/* Bit 4:ESF 5:ESFFA */
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
/* 2:ESF */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
/* 4:ESF */
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
/* 4:ESF */
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
break;
/* 9 - AMI */
case CFG_FRAME_E1PLAIN_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
break;
/* 10 - AMI */
case CFG_FRAME_E1CAS_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
break;
/* 11 - AMI */
case CFG_FRAME_E1CRC_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
break;
/* 12 - AMI */
case CFG_FRAME_E1CRC_CAS_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
break;
} /* end switch */
/*** /***
* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
@ -278,84 +296,92 @@ init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
/* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */ /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
/* note "rate bits can only be set once after reset" */ /* note "rate bits can only be set once after reset" */
if (clockmaster) if (clockmaster)
{ /* CMODE == clockMode, 0=clock master (so
* all 3 others should be slave) */
if (isT1mode) /* rate = 1.544 Mb/s */
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00); /* Comet 0 Master
* Mode(CMODE=0) */
else /* rate = 2.048 Mb/s */
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01); /* Comet 0 Master
* Mode(CMODE=0) */
/* 31: BRIF frame pulse cfg 06: tx timing options */
pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00); /* Master Mode
* i.e.FPMODE=0 (@0x20) */
if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
{ {
/* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
/* rate = 1.544 Mb/s */
if (isT1mode)
/* Comet 0 Master Mode(CMODE=0) */
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
/* rate = 2.048 Mb/s */
else
/* Comet 0 Master Mode(CMODE=0) */
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
/* 31: BRIF frame pulse cfg 06: tx timing options */
/* Master Mode i.e.FPMODE=0 (@0x20) */
pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
{
if (cxt1e1_log_level >= LOG_SBEBUG12) if (cxt1e1_log_level >= LOG_SBEBUG12)
pr_info(">> %s: clockmaster internal clock\n", __func__); pr_info(">> %s: clockmaster internal clock\n", __func__);
pci_write_32((u_int32_t *) &comet->tx_time, 0x0d); /* internal oscillator */ /* internal oscillator */
} else /* external clock source */ pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
{ } else {
/* external clock source */
if (cxt1e1_log_level >= LOG_SBEBUG12) if (cxt1e1_log_level >= LOG_SBEBUG12)
pr_info(">> %s: clockmaster external clock\n", __func__); pr_info(">> %s: clockmaster external clock\n", __func__);
pci_write_32((u_int32_t *) &comet->tx_time, 0x09); /* loop timing /* loop timing(external) */
* (external) */ pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
} }
} else /* slave */ } else {
{ /* slave */
if (isT1mode) if (isT1mode)
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20); /* Slave Mode(CMODE=1, /* Slave Mode(CMODE=1, see above) */
* see above) */ pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
else else
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21); /* Slave Mode (CMODE=1) */ /* Slave Mode(CMODE=1)*/
pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20); /* Slave Mode i.e. pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
* FPMODE=1 (@0x20) */ /* Slave Mode i.e. FPMODE=1 (@0x20) */
if (cxt1e1_log_level >= LOG_SBEBUG12) pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
pr_info(">> %s: clockslave internal clock\n", __func__); if (cxt1e1_log_level >= LOG_SBEBUG12)
pci_write_32((u_int32_t *) &comet->tx_time, 0x0d); /* oscillator timing */ pr_info(">> %s: clockslave internal clock\n", __func__);
/* oscillator timing */
pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
} }
/* 32: BRIF parity F-bit cfg */ /* 32: BRIF parity F-bit cfg */
/* Totem-pole operation */ /* Totem-pole operation */
pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01); /* Receive Backplane /* Receive Backplane Parity/F-bit */
* Parity/F-bit */ pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
/* dc: RLPS equalizer V ref */ /* dc: RLPS equalizer V ref */
/* Configuration */ /* Configuration */
if (isT1mode) if (isT1mode)
pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c); /* RLPS Equalizer /* RLPS Equalizer Voltage */
* Voltage */ pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
else else
pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34); /* RLPS Equalizer /* RLPS Equalizer Voltage */
* Voltage */ pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
/* Reserved bit set and SQUELCH enabled */ /* Reserved bit set and SQUELCH enabled */
/* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */ /* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */
pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11); /* RLPS Configuration /* RLPS Configuration Status */
* Status */ pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
if (isT1mode) if (isT1mode)
pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55); /* ? */ /* ? */
pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
else else
pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22); /* ? */ /* ? */
pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
/* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */ /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
/* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */ /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
/* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */ /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
/* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */ /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
/*** Transmit side is always an Input, Slave Clock*/ /*** Transmit side is always an Input, Slave Clock*/
/* 40: BTIF cfg 41: BTIF frame pulse cfg */ /* 40: BTIF cfg 41: loop timing(external) */
/*BTIF frame pulse cfg */
if (isT1mode) if (isT1mode)
pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38); /* BTIF Configuration /* BTIF Configuration Reg. */
* Reg. */ pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
else else
pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39); /* BTIF Configuration /* BTIF Configuration Reg. */
* Reg. */ pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
/* BTIF Frame Pulse Config. */
pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01); /* BTIF Frame Pulse pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
* Config. */
/* 0a: master diag 06: tx timing options */ /* 0a: master diag 06: tx timing options */
/* if set Comet to loop back */ /* if set Comet to loop back */
@ -367,12 +393,12 @@ init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
/* Store is enabled. */ /* Store is enabled. */
WrtXmtWaveformTbl(ci, comet, TWV_table[tix]); WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
if (isT1mode) if (isT1mode)
WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]); WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
else else
WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]); WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
SetPwrLevel (comet); SetPwrLevel(comet);
} }
/* /*
** Name: WrtXmtWaveform ** Name: WrtXmtWaveform
@ -384,12 +410,12 @@ init_comet(void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
STATIC void STATIC void
WrtXmtWaveform(ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_int8_t data) WrtXmtWaveform(ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
{ {
u_int8_t WaveformAddr; WaveformAddr;
WaveformAddr = (sample << 3) + (unit & 7); WaveformAddr = (sample << 3) + (unit & 7);
pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr); pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
pci_flush_write (ci); /* for write order preservation when /* for write order preservation when Optimizing driver */
* Optimizing driver */ pci_flush_write(ci);
pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data); pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
} }
@ -401,15 +427,15 @@ WrtXmtWaveform(ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_i
*/ */
STATIC void STATIC void
WrtXmtWaveformTbl(ci_t * ci, comet_t * comet, WrtXmtWaveformTbl(ci_t * ci, comet_t * comet,
u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]) u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
{ {
u_int32_t sample, unit; u_int32_t sample, unit;
for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
{ {
for (unit = 0; unit < COMET_NUM_UNITS; unit++) for (unit = 0; unit < COMET_NUM_UNITS; unit++)
WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]); WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
} }
/* Enable transmitter and set output amplitude */ /* Enable transmitter and set output amplitude */
pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]); pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
@ -432,55 +458,55 @@ WrtRcvEqualizerTbl(ci_t * ci, comet_t * comet, u_int32_t *table)
u_int32_t ramaddr; u_int32_t ramaddr;
volatile u_int32_t value; volatile u_int32_t value;
for (ramaddr = 0; ramaddr < 256; ramaddr++) for (ramaddr = 0; ramaddr < 256; ramaddr++) {
{ /*** the following lines are per Errata 7, 2.5 ***/
/*** the following lines are per Errata 7, 2.5 ***/ {
{ /* Set up for a read operation */
pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80); /* Set up for a read pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
* operation */ /* for write order preservation when Optimizing driver */
pci_flush_write(ci); /* for write order preservation when pci_flush_write(ci);
* Optimizing driver */ /* write the addr, initiate a read */
pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr, pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
* initiate a read */ /* for write order preservation when Optimizing driver */
pci_flush_write (ci); /* for write order preservation when pci_flush_write(ci);
* Optimizing driver */ /*
/* * wait 3 line rate clock cycles to ensure address bits are
* wait 3 line rate clock cycles to ensure address bits are * captured by T1/E1 clock
* captured by T1/E1 clock */
*/
OS_uwait(4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
* use 4us) */ OS_uwait(4, "wret");
} }
value = *table++; value = *table++;
pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24)); pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16)); pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8)); pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value); pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
pci_flush_write(ci); /* for write order preservation when /* for write order preservation when Optimizing driver */
* Optimizing driver */ pci_flush_write(ci);
/* Storing RAM address, causes RAM to be updated */ /* Storing RAM address, causes RAM to be updated */
pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0); /* Set up for a write /* Set up for a write operation */
* operation */ pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
pci_flush_write(ci); /* for write order preservation when /* for write order preservation when optimizing driver */
* Optimizing driver */ pci_flush_write(ci);
pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr, /* write the addr, initiate a read */
* initiate a read */ pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
pci_flush_write(ci); /* for write order preservation when /* for write order preservation when optimizing driver */
* Optimizing driver */ pci_flush_write(ci);
/*
* wait 3 line rate clock cycles to ensure address bits are captured /*
* by T1/E1 clock * wait 3 line rate clock cycles to ensure address bits are captured
*/ * by T1/E1 clock
OS_uwait(4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but */
* use 4us) */ /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
OS_uwait(4, "wret")
} }
pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB); /* Enable Equalizer & /* Enable Equalizer & set it to use 256 periods */
* set it to use 256 pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
* periods */
} }
@ -507,22 +533,20 @@ SetPwrLevel(comet_t * comet)
** Repeat these steps for register F5 ** Repeat these steps for register F5
** Write 0x01 to register F6 ** Write 0x01 to register F6
*/ */
pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00); /* XLPG Fuse Data Select */ /* XLPG Fuse Data Select */
pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); /* XLPG Analog Test /* XLPG Analog Test Positive control */
* Positive control */ pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe; temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp); pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); /* XLPG Analog Test
* Negative control */
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
/* XLPG Analog Test Negative control */
temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe; temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp); pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01); /* XLPG */ /* XLPG */
pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
} }
@ -541,26 +565,23 @@ SetCometOps(comet_t * comet)
if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
{ {
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg); /* read the BRIF /* read the BRIF Configuration */
* Configuration */ rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
rd_value &= ~0x20; rd_value &= ~0x20;
pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value); pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
/* read the BRIF Frame Pulse Configuration */
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
* Pulse Configuration */
rd_value &= ~0x20; rd_value &= ~0x20;
pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value); pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
} else } else {
{ /* read the BRIF Configuration */
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg); /* read the BRIF rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
* Configuration */ rd_value |= 0x20;
rd_value |= 0x20; pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value); /* read the BRIF Frame Pulse Configuration */
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame rd_value |= 0x20;
* Pulse Configuration */ pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
rd_value |= 0x20;
pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
} }
} }
#endif #endif