s390/alternatives: make use of asm_inline
This is the s390 version of commit40576e5e63
("x86: alternative.h: use asm_inline for all alternative variants"). See commiteb11186930
("compiler-types.h: add asm_inline definition") for more details. With this change the compiler will not generate many out-of-line versions for the three instruction sized arch_spin_unlock() function anymore. Due to this gcc seems to change a lot of other inline decisions which results in a net 6k text size growth according to bloat-o-meter (gcc 9.2 with defconfig). But that's still better than having many out-of-line versions of arch_spin_unlock(). Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
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6a3035dac6
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cceb018377
arch/s390
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@ -139,10 +139,10 @@ void apply_alternatives(struct alt_instr *start, struct alt_instr *end);
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* without volatile and memory clobber.
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* without volatile and memory clobber.
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*/
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*/
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#define alternative(oldinstr, altinstr, facility) \
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#define alternative(oldinstr, altinstr, facility) \
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asm volatile(ALTERNATIVE(oldinstr, altinstr, facility) : : : "memory")
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asm_inline volatile(ALTERNATIVE(oldinstr, altinstr, facility) : : : "memory")
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#define alternative_2(oldinstr, altinstr1, facility1, altinstr2, facility2) \
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#define alternative_2(oldinstr, altinstr1, facility1, altinstr2, facility2) \
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asm volatile(ALTERNATIVE_2(oldinstr, altinstr1, facility1, \
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asm_inline volatile(ALTERNATIVE_2(oldinstr, altinstr1, facility1, \
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altinstr2, facility2) ::: "memory")
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altinstr2, facility2) ::: "memory")
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLY__ */
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@ -85,7 +85,7 @@ static inline int arch_spin_trylock(arch_spinlock_t *lp)
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static inline void arch_spin_unlock(arch_spinlock_t *lp)
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static inline void arch_spin_unlock(arch_spinlock_t *lp)
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{
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{
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typecheck(int, lp->lock);
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typecheck(int, lp->lock);
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asm volatile(
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asm_inline volatile(
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ALTERNATIVE("", ".long 0xb2fa0070", 49) /* NIAI 7 */
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ALTERNATIVE("", ".long 0xb2fa0070", 49) /* NIAI 7 */
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" sth %1,%0\n"
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" sth %1,%0\n"
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: "=Q" (((unsigned short *) &lp->lock)[1])
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: "=Q" (((unsigned short *) &lp->lock)[1])
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@ -74,7 +74,7 @@ static inline int arch_load_niai4(int *lock)
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{
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{
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int owner;
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int owner;
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asm volatile(
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asm_inline volatile(
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ALTERNATIVE("", ".long 0xb2fa0040", 49) /* NIAI 4 */
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ALTERNATIVE("", ".long 0xb2fa0040", 49) /* NIAI 4 */
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" l %0,%1\n"
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" l %0,%1\n"
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: "=d" (owner) : "Q" (*lock) : "memory");
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: "=d" (owner) : "Q" (*lock) : "memory");
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@ -85,7 +85,7 @@ static inline int arch_cmpxchg_niai8(int *lock, int old, int new)
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{
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{
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int expected = old;
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int expected = old;
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asm volatile(
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asm_inline volatile(
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ALTERNATIVE("", ".long 0xb2fa0080", 49) /* NIAI 8 */
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ALTERNATIVE("", ".long 0xb2fa0080", 49) /* NIAI 8 */
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" cs %0,%3,%1\n"
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" cs %0,%3,%1\n"
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: "=d" (old), "=Q" (*lock)
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: "=d" (old), "=Q" (*lock)
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