staging: xillybus: Add sanity check in interrupt handler
Data arriving from the hardware is verified prior to its use. The lack of this check has never been reported to cause a problem, but it's necessary nevertheless. Signed-off-by: Eli Billauer <eli.billauer@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -267,6 +267,12 @@ irqreturn_t xillybus_isr(int irq, void *data)
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break;
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case XILLYMSG_OPCODE_FIFOEOF:
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if ((msg_channel > ep->num_channels) ||
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(msg_channel == 0) || (!msg_dir) ||
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!ep->channels[msg_channel]->num_wr_buffers) {
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malformed_message(ep, &buf[i]);
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break;
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}
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channel = ep->channels[msg_channel];
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spin_lock(&channel->wr_spinlock);
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channel->wr_eof = msg_bufno;
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