crypto: hisilicon/qm - add the "alg_qos" file node
1. Just move the code as needed. 2. Add the "alg_qos" file node in the qm debug sysfs. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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72b010dc33
commit
cc0c40c613
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@ -3125,62 +3125,6 @@ static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id)
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return 0;
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}
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static int hisi_qm_memory_init(struct hisi_qm *qm)
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{
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struct device *dev = &qm->pdev->dev;
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size_t qp_dma_size, off = 0;
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int i, ret = 0;
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#define QM_INIT_BUF(qm, type, num) do { \
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(qm)->type = ((qm)->qdma.va + (off)); \
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(qm)->type##_dma = (qm)->qdma.dma + (off); \
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off += QMC_ALIGN(sizeof(struct qm_##type) * (num)); \
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} while (0)
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idr_init(&qm->qp_idr);
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qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_EQ_DEPTH) +
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QMC_ALIGN(sizeof(struct qm_aeqe) * QM_Q_DEPTH) +
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QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
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QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
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qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, &qm->qdma.dma,
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GFP_ATOMIC);
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dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);
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if (!qm->qdma.va)
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return -ENOMEM;
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QM_INIT_BUF(qm, eqe, QM_EQ_DEPTH);
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QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH);
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QM_INIT_BUF(qm, sqc, qm->qp_num);
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QM_INIT_BUF(qm, cqc, qm->qp_num);
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qm->qp_array = kcalloc(qm->qp_num, sizeof(struct hisi_qp), GFP_KERNEL);
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if (!qm->qp_array) {
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ret = -ENOMEM;
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goto err_alloc_qp_array;
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}
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/* one more page for device or qp statuses */
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qp_dma_size = qm->sqe_size * QM_Q_DEPTH +
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sizeof(struct qm_cqe) * QM_Q_DEPTH;
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qp_dma_size = PAGE_ALIGN(qp_dma_size);
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for (i = 0; i < qm->qp_num; i++) {
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ret = hisi_qp_memory_init(qm, qp_dma_size, i);
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if (ret)
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goto err_init_qp_mem;
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dev_dbg(dev, "allocate qp dma buf size=%zx)\n", qp_dma_size);
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}
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return ret;
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err_init_qp_mem:
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hisi_qp_memory_uninit(qm, i);
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err_alloc_qp_array:
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dma_free_coherent(dev, qm->qdma.size, qm->qdma.va, qm->qdma.dma);
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return ret;
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}
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static void hisi_qm_pre_init(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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@ -3661,79 +3605,6 @@ static int qm_debugfs_atomic64_get(void *data, u64 *val)
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DEFINE_DEBUGFS_ATTRIBUTE(qm_atomic64_ops, qm_debugfs_atomic64_get,
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qm_debugfs_atomic64_set, "%llu\n");
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/**
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* hisi_qm_debug_init() - Initialize qm related debugfs files.
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* @qm: The qm for which we want to add debugfs files.
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*
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* Create qm related debugfs files.
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*/
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void hisi_qm_debug_init(struct hisi_qm *qm)
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{
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struct qm_dfx *dfx = &qm->debug.dfx;
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struct dentry *qm_d;
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void *data;
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int i;
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qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
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qm->debug.qm_d = qm_d;
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/* only show this in PF */
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if (qm->fun_type == QM_HW_PF) {
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qm_create_debugfs_file(qm, qm->debug.debug_root, CURRENT_QM);
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for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++)
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qm_create_debugfs_file(qm, qm_d, i);
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}
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debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);
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debugfs_create_file("cmd", 0444, qm->debug.qm_d, qm, &qm_cmd_fops);
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debugfs_create_file("status", 0444, qm->debug.qm_d, qm,
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&qm_status_fops);
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for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) {
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data = (atomic64_t *)((uintptr_t)dfx + qm_dfx_files[i].offset);
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debugfs_create_file(qm_dfx_files[i].name,
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0644,
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qm_d,
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data,
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&qm_atomic64_ops);
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}
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}
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EXPORT_SYMBOL_GPL(hisi_qm_debug_init);
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/**
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* hisi_qm_debug_regs_clear() - clear qm debug related registers.
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* @qm: The qm for which we want to clear its debug registers.
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*/
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void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
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{
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struct qm_dfx_registers *regs;
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int i;
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/* clear current_qm */
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writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
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writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
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/* clear current_q */
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writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
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writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
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/*
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* these registers are reading and clearing, so clear them after
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* reading them.
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*/
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writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
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regs = qm_dfx_regs;
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for (i = 0; i < CNT_CYC_REGS_NUM; i++) {
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readl(qm->io_base + regs->reg_offset);
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regs++;
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}
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writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
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}
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EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear);
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static void qm_hw_error_init(struct hisi_qm *qm)
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{
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struct hisi_qm_err_info *err_info = &qm->err_info;
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@ -4132,6 +4003,83 @@ static void hisi_qm_set_algqos_init(struct hisi_qm *qm)
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qm, &qm_algqos_fops);
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}
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/**
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* hisi_qm_debug_init() - Initialize qm related debugfs files.
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* @qm: The qm for which we want to add debugfs files.
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*
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* Create qm related debugfs files.
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*/
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void hisi_qm_debug_init(struct hisi_qm *qm)
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{
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struct qm_dfx *dfx = &qm->debug.dfx;
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struct dentry *qm_d;
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void *data;
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int i;
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qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
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qm->debug.qm_d = qm_d;
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/* only show this in PF */
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if (qm->fun_type == QM_HW_PF) {
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qm_create_debugfs_file(qm, qm->debug.debug_root, CURRENT_QM);
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for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++)
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qm_create_debugfs_file(qm, qm->debug.qm_d, i);
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}
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debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);
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debugfs_create_file("cmd", 0600, qm->debug.qm_d, qm, &qm_cmd_fops);
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debugfs_create_file("status", 0444, qm->debug.qm_d, qm,
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&qm_status_fops);
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for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) {
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data = (atomic64_t *)((uintptr_t)dfx + qm_dfx_files[i].offset);
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debugfs_create_file(qm_dfx_files[i].name,
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0644,
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qm_d,
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data,
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&qm_atomic64_ops);
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}
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if (qm->ver >= QM_HW_V3)
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hisi_qm_set_algqos_init(qm);
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}
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EXPORT_SYMBOL_GPL(hisi_qm_debug_init);
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/**
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* hisi_qm_debug_regs_clear() - clear qm debug related registers.
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* @qm: The qm for which we want to clear its debug registers.
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*/
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void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
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{
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struct qm_dfx_registers *regs;
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int i;
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/* clear current_qm */
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writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
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writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
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/* clear current_q */
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writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
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writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
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/*
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* these registers are reading and clearing, so clear them after
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* reading them.
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*/
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writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
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regs = qm_dfx_regs;
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for (i = 0; i < CNT_CYC_REGS_NUM; i++) {
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readl(qm->io_base + regs->reg_offset);
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regs++;
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}
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/* clear clear_enable */
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writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
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}
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EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear);
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/**
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* hisi_qm_sriov_enable() - enable virtual functions
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* @pdev: the PCIe device
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@ -5369,6 +5317,84 @@ err_disable_pcidev:
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return ret;
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}
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static int hisi_qp_alloc_memory(struct hisi_qm *qm)
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{
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struct device *dev = &qm->pdev->dev;
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size_t qp_dma_size;
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int i, ret;
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qm->qp_array = kcalloc(qm->qp_num, sizeof(struct hisi_qp), GFP_KERNEL);
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if (!qm->qp_array)
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return -ENOMEM;
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/* one more page for device or qp statuses */
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qp_dma_size = qm->sqe_size * QM_Q_DEPTH +
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sizeof(struct qm_cqe) * QM_Q_DEPTH;
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qp_dma_size = PAGE_ALIGN(qp_dma_size) + PAGE_SIZE;
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for (i = 0; i < qm->qp_num; i++) {
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ret = hisi_qp_memory_init(qm, qp_dma_size, i);
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if (ret)
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goto err_init_qp_mem;
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dev_dbg(dev, "allocate qp dma buf size=%zx)\n", qp_dma_size);
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}
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return 0;
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err_init_qp_mem:
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hisi_qp_memory_uninit(qm, i);
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return ret;
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}
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static int hisi_qm_memory_init(struct hisi_qm *qm)
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{
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struct device *dev = &qm->pdev->dev;
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int ret, total_vfs;
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size_t off = 0;
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total_vfs = pci_sriov_get_totalvfs(qm->pdev);
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qm->factor = kcalloc(total_vfs + 1, sizeof(struct qm_shaper_factor), GFP_KERNEL);
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if (!qm->factor)
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return -ENOMEM;
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#define QM_INIT_BUF(qm, type, num) do { \
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(qm)->type = ((qm)->qdma.va + (off)); \
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(qm)->type##_dma = (qm)->qdma.dma + (off); \
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off += QMC_ALIGN(sizeof(struct qm_##type) * (num)); \
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} while (0)
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idr_init(&qm->qp_idr);
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qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_EQ_DEPTH) +
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QMC_ALIGN(sizeof(struct qm_aeqe) * QM_Q_DEPTH) +
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QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
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QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
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qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, &qm->qdma.dma,
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GFP_ATOMIC);
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dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);
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if (!qm->qdma.va) {
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ret = -ENOMEM;
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goto err_alloc_qdma;
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}
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QM_INIT_BUF(qm, eqe, QM_EQ_DEPTH);
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QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH);
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QM_INIT_BUF(qm, sqc, qm->qp_num);
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QM_INIT_BUF(qm, cqc, qm->qp_num);
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ret = hisi_qp_alloc_memory(qm);
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if (ret)
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goto err_alloc_qp_array;
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return 0;
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err_alloc_qp_array:
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dma_free_coherent(dev, qm->qdma.size, qm->qdma.va, qm->qdma.dma);
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err_alloc_qdma:
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kfree(qm->factor);
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return ret;
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}
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/**
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* hisi_qm_init() - Initialize configures about qm.
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* @qm: The qm needing init.
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