ARM: sunxi: dt: add PRCM clk and reset controller subdevices
Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset controller subdevices. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -690,6 +690,44 @@
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prcm@01f01400 {
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compatible = "allwinner,sun6i-a31-prcm";
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reg = <0x01f01400 0x200>;
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ar100: ar100_clk {
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compatible = "allwinner,sun6i-a31-ar100-clk";
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#clock-cells = <0>;
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clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
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clock-output-names = "ar100";
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};
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ahb0: ahb0_clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&ar100>;
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clock-output-names = "ahb0";
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};
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apb0: apb0_clk {
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compatible = "allwinner,sun6i-a31-apb0-clk";
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#clock-cells = <0>;
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clocks = <&ahb0>;
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clock-output-names = "apb0";
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};
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apb0_gates: apb0_gates_clk {
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compatible = "allwinner,sun6i-a31-apb0-gates-clk";
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#clock-cells = <1>;
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clocks = <&apb0>;
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clock-output-names = "apb0_pio", "apb0_ir",
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"apb0_timer", "apb0_p2wi",
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"apb0_uart", "apb0_1wire",
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"apb0_i2c";
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};
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apb0_rst: apb0_rst {
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compatible = "allwinner,sun6i-a31-clock-reset";
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#reset-cells = <1>;
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};
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};
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cpucfg@01f01c00 {
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