dt-bindings: net: xlnx,axi-ethernet: convert bindings document to yaml
Convert the bindings document for Xilinx AXI Ethernet Subsystem from txt to yaml. No changes to existing binding description. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Radhey Shyam Pandey
David S. Miller
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XILINX AXI ETHERNET Device Tree Bindings
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--------------------------------------------------------
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Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
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provides connectivity to an external ethernet PHY supporting different
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interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
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segments of memory for buffering TX and RX, as well as the capability of
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offloading TX/RX checksum calculation off the processor.
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Management configuration is done through the AXI interface, while payload is
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sent and received through means of an AXI DMA controller. This driver
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includes the DMA driver code, so this driver is incompatible with AXI DMA
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driver.
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For more details about mdio please refer phy.txt file in the same directory.
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Required properties:
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- compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
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"xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
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- reg : Address and length of the IO space, as well as the address
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and length of the AXI DMA controller IO space, unless
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axistream-connected is specified, in which case the reg
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attribute of the node referenced by it is used.
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- interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
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and optionally Ethernet core. If axistream-connected is
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specified, the TX/RX DMA interrupts should be on that node
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instead, and only the Ethernet core interrupt is optionally
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specified here.
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- phy-handle : Should point to the external phy device if exists. Pointing
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this to the PCS/PMA PHY is deprecated and should be avoided.
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See ethernet.txt file in the same directory.
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- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
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Optional properties:
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- phy-mode : See ethernet.txt
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- xlnx,phy-type : Deprecated, do not use, but still accepted in preference
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to phy-mode.
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- xlnx,txcsum : 0 or empty for disabling TX checksum offload,
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1 to enable partial TX checksum offload,
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2 to enable full TX checksum offload
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- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
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- xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to
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support both 1000BaseX and SGMII modes. If set, the phy-mode
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should be set to match the mode selected on core reset (i.e.
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by the basex_or_sgmii core input line).
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- clock-names: Tuple listing input clock names. Possible clocks:
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s_axi_lite_clk: Clock for AXI register slave interface
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axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
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ref_clk: Ethernet reference clock, used by signal delay
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primitives and transceivers
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mgt_clk: MGT reference clock (used by optional internal
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PCS/PMA PHY)
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Note that if s_axi_lite_clk is not specified by name, the
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first clock of any name is used for this. If that is also not
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specified, the clock rate is auto-detected from the CPU clock
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(but only on platforms where this is possible). New device
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trees should specify all applicable clocks by name - the
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fallbacks to an unnamed clock or to CPU clock are only for
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backward compatibility.
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- clocks: Phandles to input clocks matching clock-names. Refer to common
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clock bindings.
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- axistream-connected: Reference to another node which contains the resources
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for the AXI DMA controller used by this device.
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If this is specified, the DMA-related resources from that
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device (DMA registers and DMA TX/RX interrupts) rather
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than this one will be used.
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- mdio : Child node for MDIO bus. Must be defined if PHY access is
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required through the core's MDIO interface (i.e. always,
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unless the PHY is accessed through a different bus).
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Non-standard MDIO bus frequency is supported via
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"clock-frequency", see mdio.yaml.
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- pcs-handle: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
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modes, where "pcs-handle" should be used to point
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to the PCS/PMA PHY, and "phy-handle" should point to an
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external PHY if exists.
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Example:
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axi_ethernet_eth: ethernet@40c00000 {
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compatible = "xlnx,axi-ethernet-1.00.a";
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device_type = "network";
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interrupt-parent = <µblaze_0_axi_intc>;
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interrupts = <2 0 1>;
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clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
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clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
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phy-mode = "mii";
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reg = <0x40c00000 0x40000 0x50c00000 0x40000>;
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xlnx,rxcsum = <0x2>;
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xlnx,rxmem = <0x800>;
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xlnx,txcsum = <0x2>;
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phy-handle = <&phy0>;
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axi_ethernetlite_0_mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: phy@0 {
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device_type = "ethernet-phy";
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reg = <1>;
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};
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};
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};
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@ -0,0 +1,183 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: AXI 1G/2.5G Ethernet Subsystem
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description: |
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Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
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provides connectivity to an external ethernet PHY supporting different
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interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
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segments of memory for buffering TX and RX, as well as the capability of
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offloading TX/RX checksum calculation off the processor.
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Management configuration is done through the AXI interface, while payload is
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sent and received through means of an AXI DMA controller. This driver
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includes the DMA driver code, so this driver is incompatible with AXI DMA
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driver.
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maintainers:
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- Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
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properties:
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compatible:
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enum:
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- xlnx,axi-ethernet-1.00.a
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- xlnx,axi-ethernet-1.01.a
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- xlnx,axi-ethernet-2.01.a
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reg:
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description:
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Address and length of the IO space, as well as the address
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and length of the AXI DMA controller IO space, unless
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axistream-connected is specified, in which case the reg
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attribute of the node referenced by it is used.
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maxItems: 2
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interrupts:
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items:
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- description: Ethernet core interrupt
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- description: Tx DMA interrupt
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- description: Rx DMA interrupt
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description:
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Ethernet core interrupt is optional. If axistream-connected property is
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present DMA node should contains TX/RX DMA interrupts else DMA interrupt
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resources are mentioned on ethernet node.
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minItems: 1
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phy-handle: true
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xlnx,rxmem:
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description:
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Set to allocated memory buffer for Rx/Tx in the hardware.
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$ref: /schemas/types.yaml#/definitions/uint32
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phy-mode:
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enum:
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- mii
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- gmii
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- rgmii
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- sgmii
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- 1000BaseX
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xlnx,phy-type:
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description:
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Do not use, but still accepted in preference to phy-mode.
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deprecated: true
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$ref: /schemas/types.yaml#/definitions/uint32
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xlnx,txcsum:
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description:
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TX checksum offload. 0 or empty for disabling TX checksum offload,
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1 to enable partial TX checksum offload and 2 to enable full TX
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checksum offload.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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xlnx,rxcsum:
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description:
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RX checksum offload. 0 or empty for disabling RX checksum offload,
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1 to enable partial RX checksum offload and 2 to enable full RX
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checksum offload.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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xlnx,switch-x-sgmii:
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type: boolean
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description:
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Indicate the Ethernet core is configured to support both 1000BaseX and
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SGMII modes. If set, the phy-mode should be set to match the mode
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selected on core reset (i.e. by the basex_or_sgmii core input line).
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clocks:
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items:
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- description: Clock for AXI register slave interface.
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- description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
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- description: Ethernet reference clock, used by signal delay primitives
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and transceivers.
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- description: MGT reference clock (used by optional internal PCS/PMA PHY)
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clock-names:
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items:
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- const: s_axi_lite_clk
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- const: axis_clk
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- const: ref_clk
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- const: mgt_clk
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axistream-connected:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Phandle of AXI DMA controller which contains the resources
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used by this device. If this is specified, the DMA-related resources
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from that device (DMA registers and DMA TX/RX interrupts) rather than
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this one will be used.
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mdio:
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type: object
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pcs-handle:
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description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
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modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
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and "phy-handle" should point to an external PHY if exists.
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maxItems: 1
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required:
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- compatible
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- interrupts
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- reg
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- xlnx,rxmem
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- phy-handle
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allOf:
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- $ref: /schemas/net/ethernet-controller.yaml#
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additionalProperties: false
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examples:
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- |
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axi_ethernet_eth: ethernet@40c00000 {
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compatible = "xlnx,axi-ethernet-1.00.a";
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interrupts = <2 0 1>;
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clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
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clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
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phy-mode = "mii";
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reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>;
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xlnx,rxcsum = <0x2>;
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xlnx,rxmem = <0x800>;
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xlnx,txcsum = <0x2>;
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@1 {
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device_type = "ethernet-phy";
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reg = <1>;
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};
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};
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};
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- |
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axi_ethernet_eth1: ethernet@40000000 {
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compatible = "xlnx,axi-ethernet-1.00.a";
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interrupts = <0>;
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clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
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clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
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phy-mode = "mii";
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reg = <0x00 0x40000000 0x00 0x40000>;
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xlnx,rxcsum = <0x2>;
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xlnx,rxmem = <0x800>;
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xlnx,txcsum = <0x2>;
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phy-handle = <&phy1>;
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axistream-connected = <&dma>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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device_type = "ethernet-phy";
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reg = <1>;
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};
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};
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};
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@ -23144,6 +23144,7 @@ F: drivers/iio/adc/xilinx-ams.c
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XILINX AXI ETHERNET DRIVER
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M: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
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S: Maintained
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F: Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml
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F: drivers/net/ethernet/xilinx/xilinx_axienet*
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XILINX CAN DRIVER
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