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drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 

There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5a ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").

The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
This commit is contained in:
Yakir Yang 2016-06-29 17:15:05 +08:00
parent d9c900b027
commit cb5571fcf8
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
View File

@ -163,8 +163,8 @@
#define HSYNC_POLARITY_CFG (0x1 << 0)
/* ANALOGIX_DP_PLL_REG_1 */
#define REF_CLK_24M (0x1 << 1)
#define REF_CLK_27M (0x0 << 1)
#define REF_CLK_24M (0x1 << 0)
#define REF_CLK_27M (0x0 << 0)
/* ANALOGIX_DP_LANE_MAP */
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)