usb: gadget: bdc: use the BIT macro to define bit filed
Prefer using the BIT macro to define bit fileds Cc: Florian Fainelli <f.fainelli@gmail.com> Reported-by: kernel test robot <lkp@intel.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Felipe Balbi <balbi@kernel.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/1610505748-30616-8-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Chunfeng Yun
Greg Kroah-Hartman
parent
913a4a7d13
commit
cb387becbf
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@ -102,7 +102,7 @@
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#define BDC_SPB(p) ((p) & 0x7)
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/* BDC Capability1 */
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#define BDC_P64 (1 << 0)
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#define BDC_P64 BIT(0)
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/* BDC Command register */
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#define BDC_CMD_FH 0xe
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@ -111,7 +111,7 @@
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#define BDC_CMD_BLA 0x3
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#define BDC_CMD_EPC 0x2
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#define BDC_CMD_DVC 0x1
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#define BDC_CMD_CWS (0x1 << 5)
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#define BDC_CMD_CWS BIT(5)
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#define BDC_CMD_CST(p) (((p) & (0xf << 6))>>6)
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#define BDC_CMD_EPN(p) (((p) & 0x1f) << 10)
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#define BDC_SUB_CMD_ADD (0x1 << 17)
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@ -124,7 +124,7 @@
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#define BDC_SUB_CMD_EP_STP (0x2 << 17)
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#define BDC_SUB_CMD_EP_STL (0x4 << 17)
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#define BDC_SUB_CMD_EP_RST (0x1 << 17)
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#define BDC_CMD_SRD (1 << 27)
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#define BDC_CMD_SRD BIT(27)
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/* CMD completion status */
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#define BDC_CMDS_SUCC 0x1
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@ -141,19 +141,19 @@
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#define EPM_SHIFT 4
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/* BDC USPSC */
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#define BDC_VBC (1 << 31)
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#define BDC_PRC (1 << 30)
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#define BDC_PCE (1 << 29)
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#define BDC_CFC (1 << 28)
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#define BDC_PCC (1 << 27)
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#define BDC_PSC (1 << 26)
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#define BDC_VBS (1 << 25)
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#define BDC_PRS (1 << 24)
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#define BDC_PCS (1 << 23)
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#define BDC_VBC BIT(31)
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#define BDC_PRC BIT(30)
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#define BDC_PCE BIT(29)
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#define BDC_CFC BIT(28)
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#define BDC_PCC BIT(27)
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#define BDC_PSC BIT(26)
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#define BDC_VBS BIT(25)
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#define BDC_PRS BIT(24)
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#define BDC_PCS BIT(23)
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#define BDC_PSP(p) (((p) & (0x7 << 20))>>20)
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#define BDC_SCN (1 << 8)
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#define BDC_SDC (1 << 7)
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#define BDC_SWS (1 << 4)
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#define BDC_SCN BIT(8)
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#define BDC_SDC BIT(7)
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#define BDC_SWS BIT(4)
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#define BDC_USPSC_RW (BDC_SCN|BDC_SDC|BDC_SWS|0xf)
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#define BDC_PSP(p) (((p) & (0x7 << 20))>>20)
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@ -167,17 +167,17 @@
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#define BDC_PST_MASK 0xf
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/* USPPMS */
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#define BDC_U2E (0x1 << 31)
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#define BDC_U1E (0x1 << 30)
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#define BDC_U2A (0x1 << 29)
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#define BDC_PORT_W1S (0x1 << 17)
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#define BDC_U2E BIT(31)
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#define BDC_U1E BIT(30)
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#define BDC_U2A BIT(29)
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#define BDC_PORT_W1S BIT(17)
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#define BDC_U1T(p) ((p) & 0xff)
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#define BDC_U2T(p) (((p) & 0xff) << 8)
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#define BDC_U1T_MASK 0xff
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/* USBPM2 */
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/* Hardware LPM Enable */
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#define BDC_HLE (1 << 16)
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#define BDC_HLE BIT(16)
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/* BDC Status and Control */
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#define BDC_COP_RST (1 << 29)
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@ -186,11 +186,11 @@
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#define BDC_COP_MASK (BDC_COP_RST|BDC_COP_RUN|BDC_COP_STP)
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#define BDC_COS (1 << 28)
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#define BDC_COS BIT(28)
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#define BDC_CSTS(p) (((p) & (0x7 << 20)) >> 20)
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#define BDC_MASK_MCW (1 << 7)
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#define BDC_GIE (1 << 1)
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#define BDC_GIP (1 << 0)
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#define BDC_MASK_MCW BIT(7)
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#define BDC_GIE BIT(1)
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#define BDC_GIP BIT(0)
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#define BDC_HLT 1
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#define BDC_NOR 2
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@ -201,19 +201,19 @@
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#define BD_CHAIN 0xf
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#define BD_TFS_SHIFT 4
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#define BD_SOT (1 << 26)
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#define BD_EOT (1 << 27)
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#define BD_ISP (1 << 29)
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#define BD_IOC (1 << 30)
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#define BD_SBF (1 << 31)
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#define BD_SOT BIT(26)
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#define BD_EOT BIT(27)
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#define BD_ISP BIT(29)
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#define BD_IOC BIT(30)
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#define BD_SBF BIT(31)
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#define BD_INTR_TARGET(p) (((p) & 0x1f) << 27)
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#define BDC_SRR_RWS (1 << 4)
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#define BDC_SRR_RST (1 << 3)
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#define BDC_SRR_ISR (1 << 2)
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#define BDC_SRR_IE (1 << 1)
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#define BDC_SRR_IP (1 << 0)
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#define BDC_SRR_RWS BIT(4)
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#define BDC_SRR_RST BIT(3)
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#define BDC_SRR_ISR BIT(2)
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#define BDC_SRR_IE BIT(1)
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#define BDC_SRR_IP BIT(0)
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#define BDC_SRR_EPI(p) (((p) & (0xff << 24)) >> 24)
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#define BDC_SRR_DPI(p) (((p) & (0xff << 16)) >> 16)
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#define BDC_SRR_DPI_MASK 0x00ff0000
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@ -221,7 +221,7 @@
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#define MARK_CHAIN_BD (BD_CHAIN|BD_EOT|BD_SOT)
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/* Control transfer BD specific fields */
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#define BD_DIR_IN (1 << 25)
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#define BD_DIR_IN BIT(25)
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#define BDC_PTC_MASK 0xf0000000
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@ -241,13 +241,13 @@
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/* Transfer BD fields */
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#define BD_LEN(p) ((p) & 0x1ffff)
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#define BD_LTF (1 << 25)
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#define BD_LTF BIT(25)
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#define BD_TYPE_DS 0x1
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#define BD_TYPE_SS 0x2
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#define BDC_EP_ENABLED (1 << 0)
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#define BDC_EP_STALL (1 << 1)
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#define BDC_EP_STOP (1 << 2)
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#define BDC_EP_ENABLED BIT(0)
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#define BDC_EP_STALL BIT(1)
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#define BDC_EP_STOP BIT(2)
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/* One BD can transfer max 65536 bytes */
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#define BD_MAX_BUFF_SIZE (1 << 16)
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@ -266,9 +266,9 @@
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/* FUNCTION WAKE DEV NOTIFICATION interval, USB3 spec table 8.13 */
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#define BDC_TNOTIFY 2500 /*in ms*/
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/* Devstatus bitfields */
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#define REMOTE_WAKEUP_ISSUED (1 << 16)
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#define DEVICE_SUSPENDED (1 << 17)
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#define FUNC_WAKE_ISSUED (1 << 18)
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#define REMOTE_WAKEUP_ISSUED BIT(16)
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#define DEVICE_SUSPENDED BIT(17)
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#define FUNC_WAKE_ISSUED BIT(18)
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#define REMOTE_WAKE_ENABLE (1 << USB_DEVICE_REMOTE_WAKEUP)
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/* On disconnect, preserve these bits and clear rest */
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