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@ -40,6 +40,7 @@ enum {
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struct rt5663_priv {
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struct snd_soc_codec *codec;
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struct rt5663_platform_data pdata;
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struct regmap *regmap;
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struct delayed_work jack_detect_work;
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struct snd_soc_jack *hs_jack;
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@ -57,6 +58,11 @@ struct rt5663_priv {
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int jack_type;
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};
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static const struct reg_sequence rt5663_patch_list[] = {
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{ 0x002a, 0x8020 },
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{ 0x0086, 0x0028 },
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};
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static const struct reg_default rt5663_v2_reg[] = {
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{ 0x0000, 0x0000 },
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{ 0x0001, 0xc8c8 },
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@ -476,7 +482,7 @@ static const struct reg_default rt5663_reg[] = {
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{ 0x0023, 0x0039 },
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{ 0x0026, 0xc0c0 },
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{ 0x0029, 0x8080 },
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{ 0x002a, 0xa0a0 },
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{ 0x002a, 0x8020 },
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{ 0x002c, 0x000c },
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{ 0x002d, 0x0000 },
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{ 0x0040, 0x0808 },
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@ -504,7 +510,7 @@ static const struct reg_default rt5663_reg[] = {
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{ 0x0082, 0x0000 },
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{ 0x0083, 0x0000 },
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{ 0x0084, 0x0000 },
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{ 0x0086, 0x0008 },
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{ 0x0086, 0x0028 },
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{ 0x0087, 0x0000 },
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{ 0x008a, 0x0000 },
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{ 0x008b, 0x0000 },
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@ -1508,7 +1514,7 @@ static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
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static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
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{
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struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
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int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
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int val, i = 0;
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dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
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@ -1543,25 +1549,68 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
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RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
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snd_soc_update_bits(codec, RT5663_IRQ_1,
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RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
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while (i < 5) {
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msleep(sleep_time[i]);
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val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) &
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0x0003;
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dev_dbg(codec->dev, "%s: MX-00e7 val=%x sleep %d\n",
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__func__, val, sleep_time[i]);
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i++;
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if (val == 0x1 || val == 0x2 || val == 0x3)
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while (true) {
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regmap_read(rt5663->regmap, RT5663_INT_ST_2, &val);
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if (!(val & 0x80))
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usleep_range(10000, 10005);
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else
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break;
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if (i > 200)
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break;
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i++;
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}
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val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) & 0x0003;
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dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
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snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
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RT5663_OSW_HP_L_MASK | RT5663_OSW_HP_R_MASK,
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RT5663_OSW_HP_L_EN | RT5663_OSW_HP_R_EN);
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switch (val) {
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case 1:
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case 2:
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rt5663->jack_type = SND_JACK_HEADSET;
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rt5663_enable_push_button_irq(codec, true);
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if (rt5663->pdata.dc_offset_l_manual_mic) {
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regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
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rt5663->pdata.dc_offset_l_manual_mic >>
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16);
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regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
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rt5663->pdata.dc_offset_l_manual_mic &
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0xffff);
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}
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if (rt5663->pdata.dc_offset_r_manual_mic) {
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regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
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rt5663->pdata.dc_offset_r_manual_mic >>
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16);
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regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
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rt5663->pdata.dc_offset_r_manual_mic &
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0xffff);
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}
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break;
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default:
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rt5663->jack_type = SND_JACK_HEADPHONE;
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if (rt5663->pdata.dc_offset_l_manual) {
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regmap_write(rt5663->regmap, RT5663_MIC_DECRO_2,
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rt5663->pdata.dc_offset_l_manual >> 16);
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regmap_write(rt5663->regmap, RT5663_MIC_DECRO_3,
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rt5663->pdata.dc_offset_l_manual &
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0xffff);
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}
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if (rt5663->pdata.dc_offset_r_manual) {
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regmap_write(rt5663->regmap, RT5663_MIC_DECRO_5,
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rt5663->pdata.dc_offset_r_manual >> 16);
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regmap_write(rt5663->regmap, RT5663_MIC_DECRO_6,
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rt5663->pdata.dc_offset_r_manual &
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0xffff);
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}
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break;
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}
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} else {
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@ -1656,6 +1705,9 @@ static void rt5663_jack_detect_work(struct work_struct *work)
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default:
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dev_err(codec->dev, "Unknown CODEC Version\n");
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}
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/* Delay the jack insert report to avoid pop noise */
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msleep(30);
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} else {
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/* jack is already in, report button event */
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report = SND_JACK_HEADSET;
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@ -1953,13 +2005,9 @@ static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
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static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
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SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
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RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
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SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
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RT5663_M_DAC_R1_STO_L_SHIFT, 1, 1),
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};
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static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
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SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
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RT5663_M_DAC_L1_STO_R_SHIFT, 1, 1),
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SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
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RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
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};
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@ -2024,10 +2072,6 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
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RT5663_HP_SIG_SRC1_SILENCE);
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} else {
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snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
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0x000b);
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
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0x0030);
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snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
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RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
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snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
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@ -2036,6 +2080,8 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
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snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
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snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
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snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
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snd_soc_update_bits(codec, RT5663_STO_DRE_1, 0x8000,
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0x8000);
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
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0x3000);
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}
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@ -2050,9 +2096,36 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
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snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
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RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0);
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
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0x000b);
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}
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break;
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default:
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return 0;
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}
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return 0;
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}
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static int rt5663_charge_pump_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
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struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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if (rt5663->codec_ver == CODEC_VER_0) {
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
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0x0030);
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003,
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0x0003);
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}
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break;
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case SND_SOC_DAPM_POST_PMD:
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if (rt5663->codec_ver == CODEC_VER_0) {
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0003, 0);
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snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0);
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}
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break;
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@ -2182,6 +2255,9 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
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SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
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/* Headphone*/
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SND_SOC_DAPM_SUPPLY("HP Charge Pump", SND_SOC_NOPM, 0, 0,
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rt5663_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
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SND_SOC_DAPM_POST_PMD),
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SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
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SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
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@ -2330,14 +2406,13 @@ static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
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{ "DAC R1", NULL, "ADDA MIXR" },
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{ "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
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{ "STO1 DAC MIXL", "DAC R Switch", "DAC R1" },
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{ "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
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{ "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
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{ "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
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{ "STO1 DAC MIXR", "DAC L Switch", "DAC L1" },
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{ "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
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{ "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
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{ "HP Amp", NULL, "HP Charge Pump" },
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{ "HP Amp", NULL, "DAC L" },
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{ "HP Amp", NULL, "DAC R" },
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};
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@ -2956,7 +3031,7 @@ MODULE_DEVICE_TABLE(of, rt5663_of_match);
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#endif
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#ifdef CONFIG_ACPI
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static struct acpi_device_id rt5663_acpi_match[] = {
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static const struct acpi_device_id rt5663_acpi_match[] = {
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{ "10EC5663", 0},
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{},
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};
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@ -2986,47 +3061,76 @@ static void rt5663_calibrate(struct rt5663_priv *rt5663)
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{
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int value, count;
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regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0280);
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regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
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regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
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regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
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regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
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regmap_write(rt5663->regmap, RT5663_RESET, 0x0000);
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msleep(20);
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regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
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regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
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regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
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regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
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regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
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regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0003);
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regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
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regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1111);
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regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_4, 0x00a1);
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regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
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regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
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regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
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regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
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regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x000c);
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|
|
regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x0324);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23b);
|
|
|
|
|
msleep(30);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23b);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8000);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x0008);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_CBJ_1, 0x8c10);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_IL_CMD_2, 0x00c1);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb880);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4110);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_2, 0x4118);
|
|
|
|
|
|
|
|
|
|
count = 0;
|
|
|
|
|
while (true) {
|
|
|
|
|
regmap_read(rt5663->regmap, RT5663_INT_ST_2, &value);
|
|
|
|
|
if (!(value & 0x80))
|
|
|
|
|
usleep_range(10000, 10005);
|
|
|
|
|
else
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
if (++count > 200)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_IMP_SEN_19, 0x0000);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0038);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x8003);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x2080);
|
|
|
|
|
msleep(40);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x0000);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xabba);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xafaa);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4702);
|
|
|
|
|
msleep(200);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x1111);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4402);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x3311);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06c2);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06ce);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6800);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_2, 0x1100);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0057);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe800);
|
|
|
|
|
|
|
|
|
|
count = 0;
|
|
|
|
|
while (true) {
|
|
|
|
|
regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
|
|
|
|
@ -3039,11 +3143,56 @@ static void rt5663_calibrate(struct rt5663_priv *rt5663)
|
|
|
|
|
return;
|
|
|
|
|
count++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x6200);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_7, 0x0059);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xe200);
|
|
|
|
|
|
|
|
|
|
count = 0;
|
|
|
|
|
while (true) {
|
|
|
|
|
regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
|
|
|
|
|
if (value & 0x8000)
|
|
|
|
|
usleep_range(10000, 10005);
|
|
|
|
|
else
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
if (count > 200)
|
|
|
|
|
return;
|
|
|
|
|
count++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_EM_JACK_TYPE_1, 0xb8e0);
|
|
|
|
|
usleep_range(10000, 10005);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0x003b);
|
|
|
|
|
usleep_range(10000, 10005);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0000);
|
|
|
|
|
usleep_range(10000, 10005);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x000b);
|
|
|
|
|
usleep_range(10000, 10005);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x0008);
|
|
|
|
|
usleep_range(10000, 10005);
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0000);
|
|
|
|
|
usleep_range(10000, 10005);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rt5663_parse_dp(struct rt5663_priv *rt5663, struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
device_property_read_u32(dev, "realtek,dc_offset_l_manual",
|
|
|
|
|
&rt5663->pdata.dc_offset_l_manual);
|
|
|
|
|
device_property_read_u32(dev, "realtek,dc_offset_r_manual",
|
|
|
|
|
&rt5663->pdata.dc_offset_r_manual);
|
|
|
|
|
device_property_read_u32(dev, "realtek,dc_offset_l_manual_mic",
|
|
|
|
|
&rt5663->pdata.dc_offset_l_manual_mic);
|
|
|
|
|
device_property_read_u32(dev, "realtek,dc_offset_r_manual_mic",
|
|
|
|
|
&rt5663->pdata.dc_offset_r_manual_mic);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int rt5663_i2c_probe(struct i2c_client *i2c,
|
|
|
|
|
const struct i2c_device_id *id)
|
|
|
|
|
{
|
|
|
|
|
struct rt5663_platform_data *pdata = dev_get_platdata(&i2c->dev);
|
|
|
|
|
struct rt5663_priv *rt5663;
|
|
|
|
|
int ret;
|
|
|
|
|
unsigned int val;
|
|
|
|
@ -3057,6 +3206,11 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
|
|
|
|
|
|
|
|
|
|
i2c_set_clientdata(i2c, rt5663);
|
|
|
|
|
|
|
|
|
|
if (pdata)
|
|
|
|
|
rt5663->pdata = *pdata;
|
|
|
|
|
else
|
|
|
|
|
rt5663_parse_dp(rt5663, &i2c->dev);
|
|
|
|
|
|
|
|
|
|
regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
|
|
|
|
|
if (IS_ERR(regmap)) {
|
|
|
|
|
ret = PTR_ERR(regmap);
|
|
|
|
@ -3105,6 +3259,20 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
|
|
|
|
|
regmap_write(rt5663->regmap, RT5663_RESET, 0);
|
|
|
|
|
dev_dbg(&i2c->dev, "calibrate done\n");
|
|
|
|
|
|
|
|
|
|
switch (rt5663->codec_ver) {
|
|
|
|
|
case CODEC_VER_1:
|
|
|
|
|
break;
|
|
|
|
|
case CODEC_VER_0:
|
|
|
|
|
ret = regmap_register_patch(rt5663->regmap, rt5663_patch_list,
|
|
|
|
|
ARRAY_SIZE(rt5663_patch_list));
|
|
|
|
|
if (ret != 0)
|
|
|
|
|
dev_warn(&i2c->dev,
|
|
|
|
|
"Failed to apply regmap patch: %d\n", ret);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* GPIO1 as IRQ */
|
|
|
|
|
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
|
|
|
|
|
RT5663_GP1_PIN_IRQ);
|
|
|
|
|