UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm fixes for 5.5-rc5 

agp:
 - two unused variable removed
 
 amdgpu:
 - ATPX regression fix
 - SMU metrics table locking fixes
 - gfxoff fix for raven
 - RLC firmware loading stability fix
 
 mediatek:
 - external display fix
 - dsi timing fix
 
 sun4i:
 - Fix double-free in connector/encoder cleanup (Stefan)
 
 maildp:
 - Make vtable static (Ben)
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJeDuShAAoJEAx081l5xIa+0usQAIwwMJtgLqTjXKDqLn1h8blY
 lTmpjUX/sbMgVdKA3asoQuLEKP9ZjzQtBNAK1XodeI6u4Z/y/KJa3j6mdRr5Zz9o
 gNQgJpg66O+48mq/bXImpev3O31Avs+Ij79/eSbxwVTnQeYjORDEqw4dS+4tF6dW
 62RFuZnzPpOt9amV0a83Vjq6PutPy7z+ulpfBGc3C9F+YAEFGFRTd+u5lSS0h2wz
 FlZllBn1Joqxi2vKjymh+E9Rxzr2BEe30yx3cShXcFrRXrstkGIfTuQkkeTvmj+P
 Fohymt7D3U07p+11CA9GD2Dvbh2Zkqrj4MFLlaaNtUnJ4xz2EHb8Na6h3HJQNcTT
 xgHeQ56eMIKhQD76xC9mjJU7NHGbLjlSgmiWMD7AVEQsTpXpmPqckYPOFnRDVcuJ
 HAaHmo2KwcaG05ct1H6G4x81B9xl+kCtwzyJY9yXvndZthpUX3FuZ3p2FskkrBH2
 iDmNZLPVJ98Prz8ytvO4XvKxoFTmMUU17xZprE7gftfL031tAZYvp52rH29uDqgx
 RhprhH9O00B+Gx5KuOxro+f5kOqn0Fp/s5oSdAU8ySMGc2sngxHElfSle4AJjnaN
 78OvggBNPkrl3z8RssOkzs+AckFItVUU26horzzUy7mY6QyYz+F6HfGjlwiwzQrn
 XCc86rgW+ieYq7QXYTuq
 =H4/Q
 -----END PGP SIGNATURE-----

Merge tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "New Years fixes! Mostly amdgpu with a light smattering of arm
  graphics, and two AGP warning fixes.

  Quiet as expected, hopefully we don't get a post holiday rush.

  agp:
   - two unused variable removed

  amdgpu:
   - ATPX regression fix
   - SMU metrics table locking fixes
   - gfxoff fix for raven
   - RLC firmware loading stability fix

  mediatek:
   - external display fix
   - dsi timing fix

  sun4i:
   - Fix double-free in connector/encoder cleanup (Stefan)

  maildp:
   - Make vtable static (Ben)"

* tag 'drm-fixes-2020-01-03' of git://anongit.freedesktop.org/drm/drm:
  agp: remove unused variable arqsz in agp_3_5_enable()
  agp: remove unused variable mcapndx
  drm/amdgpu: correct RLC firmwares loading sequence
  drm/amdgpu: enable gfxoff for raven1 refresh
  drm/amdgpu/smu: add metrics table lock for vega20 (v2)
  drm/amdgpu/smu: add metrics table lock for navi (v2)
  drm/amdgpu/smu: add metrics table lock for arcturus (v2)
  drm/amdgpu/smu: add metrics table lock
  Revert "drm/amdgpu: simplify ATPX detection"
  drm/arm/mali: make malidp_mw_connector_helper_funcs static
  drm/sun4i: hdmi: Remove duplicate cleanup calls
  drm/mediatek: reduce the hbp and hfp for phy timing
  drm/mediatek: Fix can't get component for external display plane.
  drm/mediatek: Check return value of mtk_drm_ddp_comp_for_plane.
This commit is contained in:
Linus Torvalds 2020-01-03 11:08:30 -08:00
parent 15f0ec941f a6204fc7b8
commit ca78fdeb00
14 changed files with 80 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/char/agp/isoch.c
View File

@ -84,7 +84,6 @@ static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge,
unsigned int cdev = 0;
u32 mnistat, tnistat, tstatus, mcmd;
u16 tnicmd, mnicmd;
u8 mcapndx;
u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async;
u32 step, rem, rem_isoch, rem_async;
int ret = 0;
@ -138,8 +137,6 @@ static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge,
cur = list_entry(pos, struct agp_3_5_dev, list);
dev = cur->dev;
mcapndx = cur->capndx;
pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &mnistat);
master[cdev].maxbw = (mnistat >> 16) & 0xff;
@ -251,8 +248,6 @@ static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge,
cur = master[cdev].dev;
dev = cur->dev;
mcapndx = cur->capndx;
master[cdev].rq += (cdev == ndevs - 1)
? (rem_async + rem_isoch) : step;
@ -319,7 +314,7 @@ int agp_3_5_enable(struct agp_bridge_data *bridge)
{
struct pci_dev *td = bridge->dev, *dev = NULL;
u8 mcapndx;
u32 isoch, arqsz;
u32 isoch;
u32 tstatus, mstatus, ncapid;
u32 mmajor;
u16 mpstat;
@ -334,8 +329,6 @@ int agp_3_5_enable(struct agp_bridge_data *bridge)
if (isoch == 0) /* isoch xfers not available, bail out. */
return -ENODEV;
arqsz = (tstatus >> 13) & 0x7;
/*
* Allocate a head for our AGP 3.5 device list
* (multiple AGP v3 devices are allowed behind a single bridge).

12
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
View File

@ -613,7 +613,17 @@ static bool amdgpu_atpx_detect(void)
bool d3_supported = false;
struct pci_dev *parent_pdev;
while ((pdev = pci_get_class(PCI_BASE_CLASS_DISPLAY << 16, pdev)) != NULL) {
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
vga_count++;
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
parent_pdev = pci_upstream_bridge(pdev);
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
amdgpu_atpx_get_quirks(pdev);
}
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
vga_count++;
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);

2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -1488,7 +1488,7 @@ out:
/* Start rlc autoload after psp recieved all the gfx firmware */
if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM)) {
AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
ret = psp_rlc_autoload(psp);
if (ret) {
DRM_ERROR("Failed to start rlc autoload\n");

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
View File

@ -292,10 +292,10 @@ enum AMDGPU_UCODE_ID {
AMDGPU_UCODE_ID_CP_MEC2_JT,
AMDGPU_UCODE_ID_CP_MES,
AMDGPU_UCODE_ID_CP_MES_DATA,
AMDGPU_UCODE_ID_RLC_G,
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
AMDGPU_UCODE_ID_RLC_G,
AMDGPU_UCODE_ID_STORAGE,
AMDGPU_UCODE_ID_SMC,
AMDGPU_UCODE_ID_UVD,

15
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -1052,17 +1052,10 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
case CHIP_VEGA20:
break;
case CHIP_RAVEN:
/* Disable GFXOFF on original raven. There are combinations
* of sbios and platforms that are not stable.
*/
if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
&&((adev->gfx.rlc_fw_version != 106 &&
adev->gfx.rlc_fw_version < 531) ||
(adev->gfx.rlc_fw_version == 53815) ||
(adev->gfx.rlc_feature_version < 1) ||
!adev->gfx.rlc.is_rlc_v2_1))
if (!(adev->rev_id >= 0x8 ||
adev->pdev->device == 0x15d8) &&
(adev->pm.fw_version < 0x41e2b || /* not raven1 fresh */
!adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore ucodes */
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
if (adev->pm.pp_feature & PP_GFXOFF_MASK)

1
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -866,6 +866,7 @@ static int smu_sw_init(void *handle)
smu->smu_baco.platform_support = false;
mutex_init(&smu->sensor_lock);
mutex_init(&smu->metrics_lock);
smu->watermarks_bitmap = 0;
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

3
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
View File

@ -862,18 +862,21 @@ static int arcturus_get_metrics_table(struct smu_context *smu,
struct smu_table_context *smu_table= &smu->smu_table;
int ret = 0;
mutex_lock(&smu->metrics_lock);
if (!smu_table->metrics_time ||
time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
(void *)smu_table->metrics_table, false);
if (ret) {
pr_info("Failed to export SMU metrics table!\n");
mutex_unlock(&smu->metrics_lock);
return ret;
}
smu_table->metrics_time = jiffies;
}
memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
mutex_unlock(&smu->metrics_lock);
return ret;
}

1
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -349,6 +349,7 @@ struct smu_context
const struct pptable_funcs *ppt_funcs;
struct mutex mutex;
struct mutex sensor_lock;
struct mutex metrics_lock;
uint64_t pool_size;
struct smu_table_context smu_table;

3
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View File

@ -562,17 +562,20 @@ static int navi10_get_metrics_table(struct smu_context *smu,
struct smu_table_context *smu_table= &smu->smu_table;
int ret = 0;
mutex_lock(&smu->metrics_lock);
if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
(void *)smu_table->metrics_table, false);
if (ret) {
pr_info("Failed to export SMU metrics table!\n");
mutex_unlock(&smu->metrics_lock);
return ret;
}
smu_table->metrics_time = jiffies;
}
memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
mutex_unlock(&smu->metrics_lock);
return ret;
}

3
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
View File

@ -1678,17 +1678,20 @@ static int vega20_get_metrics_table(struct smu_context *smu,
struct smu_table_context *smu_table= &smu->smu_table;
int ret = 0;
mutex_lock(&smu->metrics_lock);
if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
(void *)smu_table->metrics_table, false);
if (ret) {
pr_info("Failed to export SMU metrics table!\n");
mutex_unlock(&smu->metrics_lock);
return ret;
}
smu_table->metrics_time = jiffies;
}
memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
mutex_unlock(&smu->metrics_lock);
return ret;
}

2
drivers/gpu/drm/arm/malidp_mw.c
View File

@ -56,7 +56,7 @@ malidp_mw_connector_mode_valid(struct drm_connector *connector,
return MODE_OK;
}
const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
static const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
.get_modes = malidp_mw_connector_get_modes,
.mode_valid = malidp_mw_connector_mode_valid,
};

18
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
View File

@ -215,11 +215,12 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_ddp_comp *comp;
int i, count = 0;
unsigned int local_index = plane - mtk_crtc->planes;
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
comp = mtk_crtc->ddp_comp[i];
if (plane->index < (count + mtk_ddp_comp_layer_nr(comp))) {
*local_layer = plane->index - count;
if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
*local_layer = local_index - count;
return comp;
}
count += mtk_ddp_comp_layer_nr(comp);
@ -310,7 +311,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
plane_state = to_mtk_plane_state(plane->state);
comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
mtk_ddp_comp_layer_config(comp, local_layer, plane_state);
if (comp)
mtk_ddp_comp_layer_config(comp, local_layer,
plane_state);
}
return 0;
@ -386,8 +389,9 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
&local_layer);
mtk_ddp_comp_layer_config(comp, local_layer,
plane_state);
if (comp)
mtk_ddp_comp_layer_config(comp, local_layer,
plane_state);
plane_state->pending.config = false;
}
mtk_crtc->pending_planes = false;
@ -401,7 +405,9 @@ int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_ddp_comp *comp;
comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
return mtk_ddp_comp_layer_check(comp, local_layer, state);
if (comp)
return mtk_ddp_comp_layer_check(comp, local_layer, state);
return 0;
}
static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,

67
drivers/gpu/drm/mediatek/mtk_dsi.c
View File

@ -230,28 +230,25 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
{
u32 timcon0, timcon1, timcon2, timcon3;
u32 ui, cycle_time;
u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
struct mtk_phy_timing *timing = &dsi->phy_timing;
ui = DIV_ROUND_UP(1000000000, dsi->data_rate);
cycle_time = div_u64(8000000000ULL, dsi->data_rate);
timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
timing->da_hs_prepare;
timing->da_hs_trail = timing->da_hs_prepare + 1;
timing->lpx = NS_TO_CYCLE(60, cycle_time);
timing->da_hs_prepare = NS_TO_CYCLE(50 + 5 * ui, cycle_time);
timing->da_hs_zero = NS_TO_CYCLE(110 + 6 * ui, cycle_time);
timing->da_hs_trail = NS_TO_CYCLE(77 + 4 * ui, cycle_time);
timing->ta_go = 4 * timing->lpx - 2;
timing->ta_sure = timing->lpx + 2;
timing->ta_get = 4 * timing->lpx;
timing->da_hs_exit = 2 * timing->lpx + 1;
timing->ta_go = 4 * timing->lpx;
timing->ta_sure = 3 * timing->lpx / 2;
timing->ta_get = 5 * timing->lpx;
timing->da_hs_exit = 2 * timing->lpx;
timing->clk_hs_zero = NS_TO_CYCLE(336, cycle_time);
timing->clk_hs_trail = NS_TO_CYCLE(100, cycle_time) + 10;
timing->clk_hs_prepare = NS_TO_CYCLE(64, cycle_time);
timing->clk_hs_post = NS_TO_CYCLE(80 + 52 * ui, cycle_time);
timing->clk_hs_exit = 2 * timing->lpx;
timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
timing->clk_hs_post = timing->clk_hs_prepare + 8;
timing->clk_hs_trail = timing->clk_hs_prepare;
timing->clk_hs_zero = timing->clk_hs_trail * 4;
timing->clk_hs_exit = 2 * timing->clk_hs_trail;
timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
@ -482,27 +479,39 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
dsi_tmp_buf_bpp - 10);
data_phy_cycles = timing->lpx + timing->da_hs_prepare +
timing->da_hs_zero + timing->da_hs_exit + 2;
timing->da_hs_zero + timing->da_hs_exit + 3;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
if (vm->hfront_porch * dsi_tmp_buf_bpp >
if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
data_phy_cycles * dsi->lanes + 18) {
horizontal_frontporch_byte = vm->hfront_porch *
dsi_tmp_buf_bpp -
data_phy_cycles *
dsi->lanes - 18;
horizontal_frontporch_byte =
vm->hfront_porch * dsi_tmp_buf_bpp -
(data_phy_cycles * dsi->lanes + 18) *
vm->hfront_porch /
(vm->hfront_porch + vm->hback_porch);
horizontal_backporch_byte =
horizontal_backporch_byte -
(data_phy_cycles * dsi->lanes + 18) *
vm->hback_porch /
(vm->hfront_porch + vm->hback_porch);
} else {
DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
horizontal_frontporch_byte = vm->hfront_porch *
dsi_tmp_buf_bpp;
}
} else {
if (vm->hfront_porch * dsi_tmp_buf_bpp >
if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
data_phy_cycles * dsi->lanes + 12) {
horizontal_frontporch_byte = vm->hfront_porch *
dsi_tmp_buf_bpp -
data_phy_cycles *
dsi->lanes - 12;
horizontal_frontporch_byte =
vm->hfront_porch * dsi_tmp_buf_bpp -
(data_phy_cycles * dsi->lanes + 12) *
vm->hfront_porch /
(vm->hfront_porch + vm->hback_porch);
horizontal_backporch_byte = horizontal_backporch_byte -
(data_phy_cycles * dsi->lanes + 12) *
vm->hback_porch /
(vm->hfront_porch + vm->hback_porch);
} else {
DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
horizontal_frontporch_byte = vm->hfront_porch *

2
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
View File

@ -685,8 +685,6 @@ static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
cec_unregister_adapter(hdmi->cec_adap);
drm_connector_cleanup(&hdmi->connector);
drm_encoder_cleanup(&hdmi->encoder);
i2c_del_adapter(hdmi->i2c);
i2c_put_adapter(hdmi->ddc_i2c);
clk_disable_unprepare(hdmi->mod_clk);