liquidio CN23XX: sysfs VF config support
Adds sysfs based support for enabling or disabling VFs. Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -180,6 +180,10 @@ struct octeon_device_priv {
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unsigned long napi_mask;
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};
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#ifdef CONFIG_PCI_IOV
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static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs);
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#endif
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static int octeon_device_init(struct octeon_device *);
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static int liquidio_stop(struct net_device *netdev);
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static void liquidio_remove(struct pci_dev *pdev);
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@ -518,6 +522,9 @@ static struct pci_driver liquidio_pci_driver = {
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.suspend = liquidio_suspend,
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.resume = liquidio_resume,
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#endif
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#ifdef CONFIG_PCI_IOV
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.sriov_configure = liquidio_enable_sriov,
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#endif
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};
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/**
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@ -1472,6 +1479,10 @@ static void octeon_destroy_resources(struct octeon_device *oct)
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continue;
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octeon_delete_instr_queue(oct, i);
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}
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#ifdef CONFIG_PCI_IOV
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if (oct->sriov_info.sriov_enabled)
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pci_disable_sriov(oct->pci_dev);
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#endif
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/* fallthrough */
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case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
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octeon_free_sc_buffer_pool(oct);
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@ -3990,6 +4001,101 @@ setup_nic_wait_intr:
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return -ENODEV;
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}
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#ifdef CONFIG_PCI_IOV
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static int octeon_enable_sriov(struct octeon_device *oct)
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{
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unsigned int num_vfs_alloced = oct->sriov_info.num_vfs_alloced;
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struct pci_dev *vfdev;
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int err;
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u32 u;
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if (OCTEON_CN23XX_PF(oct) && num_vfs_alloced) {
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err = pci_enable_sriov(oct->pci_dev,
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oct->sriov_info.num_vfs_alloced);
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if (err) {
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dev_err(&oct->pci_dev->dev,
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"OCTEON: Failed to enable PCI sriov: %d\n",
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err);
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oct->sriov_info.num_vfs_alloced = 0;
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return err;
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}
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oct->sriov_info.sriov_enabled = 1;
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/* init lookup table that maps DPI ring number to VF pci_dev
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* struct pointer
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*/
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u = 0;
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vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
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OCTEON_CN23XX_VF_VID, NULL);
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while (vfdev) {
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if (vfdev->is_virtfn &&
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(vfdev->physfn == oct->pci_dev)) {
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oct->sriov_info.dpiring_to_vfpcidev_lut[u] =
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vfdev;
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u += oct->sriov_info.rings_per_vf;
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}
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vfdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
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OCTEON_CN23XX_VF_VID, vfdev);
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}
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}
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return num_vfs_alloced;
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}
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static int lio_pci_sriov_disable(struct octeon_device *oct)
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{
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int u;
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if (pci_vfs_assigned(oct->pci_dev)) {
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dev_err(&oct->pci_dev->dev, "VFs are still assigned to VMs.\n");
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return -EPERM;
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}
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pci_disable_sriov(oct->pci_dev);
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u = 0;
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while (u < MAX_POSSIBLE_VFS) {
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oct->sriov_info.dpiring_to_vfpcidev_lut[u] = NULL;
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u += oct->sriov_info.rings_per_vf;
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}
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oct->sriov_info.num_vfs_alloced = 0;
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dev_info(&oct->pci_dev->dev, "oct->pf_num:%d disabled VFs\n",
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oct->pf_num);
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return 0;
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}
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static int liquidio_enable_sriov(struct pci_dev *dev, int num_vfs)
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{
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struct octeon_device *oct = pci_get_drvdata(dev);
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int ret = 0;
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if ((num_vfs == oct->sriov_info.num_vfs_alloced) &&
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(oct->sriov_info.sriov_enabled)) {
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dev_info(&oct->pci_dev->dev, "oct->pf_num:%d already enabled num_vfs:%d\n",
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oct->pf_num, num_vfs);
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return 0;
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}
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if (!num_vfs) {
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ret = lio_pci_sriov_disable(oct);
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} else if (num_vfs > oct->sriov_info.max_vfs) {
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dev_err(&oct->pci_dev->dev,
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"OCTEON: Max allowed VFs:%d user requested:%d",
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oct->sriov_info.max_vfs, num_vfs);
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ret = -EPERM;
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} else {
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oct->sriov_info.num_vfs_alloced = num_vfs;
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ret = octeon_enable_sriov(oct);
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dev_info(&oct->pci_dev->dev, "oct->pf_num:%d num_vfs:%d\n",
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oct->pf_num, num_vfs);
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}
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return ret;
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}
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#endif
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/**
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* \brief initialize the NIC
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* @param oct octeon device
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@ -472,4 +472,7 @@ struct octeon_config {
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#define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
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#define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
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#define MAX_POSSIBLE_VFS 64
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#endif /* __OCTEON_CONFIG_H__ */
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@ -38,6 +38,7 @@
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#define OCTEON_CN68XX 0x0091
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#define OCTEON_CN66XX 0x0092
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#define OCTEON_CN23XX_PF_VID 0x9702
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#define OCTEON_CN23XX_VF_VID 0x9712
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/**RevisionId for the chips */
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#define OCTEON_CN23XX_REV_1_0 0x00
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@ -331,6 +332,9 @@ struct octeon_sriov_info {
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**/
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u32 max_vfs;
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/** Number of VF devices enabled using sysfs. */
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u32 num_vfs_alloced;
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/* Actual rings left for PF device */
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u32 num_pf_rings;
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@ -340,6 +344,10 @@ struct octeon_sriov_info {
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/* total pf rings */
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u32 trs;
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u32 sriov_enabled;
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/*lookup table that maps DPI ring number to VF pci_dev struct pointer*/
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struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS];
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};
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struct octeon_ioq_vector {
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