nvme fixes for Linux 5.19
- set controller enable bit in a separate write (Niklas Cassel) - disable namespace identifiers for the MAXIO MAP1001 (me) - fix a comment typo (Julia Lawall) -----BEGIN PGP SIGNATURE----- iQI/BAABCgApFiEEgdbnc3r/njty3Iq9D55TZVIEUYMFAmKYSRALHGhjaEBsc3Qu ZGUACgkQD55TZVIEUYOTRhAAgyfTQ2mtdCdJELcIYbhSTXDljDYzY7h9HDSDzXSp q6EE9bnxU+yBFS1t33lcM8/erN2M3RW2qIw2/pCSExXyGMrmg7jF8r0kDlVp2Lt9 AAq+5LOQtJ4coFl2qSD/CGJzN7Wc/53XX18X+MwbkhbNSvk4Qgn1p+wyXOk2+q+w L2lwBEWtZmkSEaXeWGPVbHTKHfOGP54FrpKUNSu0O9YnACQTx2S0FC87FV+LlLU0 dT+kpvsWTJIJZyAzvjrS4v8I2RX/BhFaCZu2WZwi6SQoSm2QGZe9GBVMUErC3iYM OzoM7rDyPfTY50VFX/mArEs9vGtPjusKypRK/rpvVx+QLsrkJkSBd78tOVy5fsCA 7geXj9OWDJDH3B+XH3otsUEDhwLkOm7Ct22eoezDYtwOt6cbiRypbgljSA/a6zdr 1c8gt1a6vLJMJUJGE3mSvqzgBHs2aNShLxQCq/SDA3nycSQfXjFr5vjLXW5eP5F6 +Hs79zNQpHHgUsE0Ew5aXUDIaKu1AQNKqsORyFEvmCrZwOYRClzDsdU5ucw33VaD 7dHDo4I2L17Dw+NPfn2xMoIYug4n/ITSOtHXnpISgsCHLNH76rrkT9uDxC7svlSq SsvQSfHSU5vkdQEuQoMW61AodtKkB1t+pIeS80MAO/Cf2ABfJP5ndFbXwrqxnJZP 530= =IvA5 -----END PGP SIGNATURE----- Merge tag 'nvme-5.19-2022-06-02' of git://git.infradead.org/nvme into for-5.19/drivers Pull NVMe fixes from Christoph: "nvme fixes for Linux 5.19 - set controller enable bit in a separate write (Niklas Cassel) - disable namespace identifiers for the MAXIO MAP1001 (me) - fix a comment typo (Julia Lawall)" * tag 'nvme-5.19-2022-06-02' of git://git.infradead.org/nvme: nvmet: fix typo in comment nvme: set controller enable bit in a separate write nvme-pci: disable namespace identifiers for the MAXIO MAP1001
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c9fdf7b453
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@ -2227,8 +2227,16 @@ int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
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ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
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ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
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ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
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ctrl->ctrl_config |= NVME_CC_ENABLE;
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ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
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if (ret)
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return ret;
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/* Flush write to device (required if transport is PCI) */
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ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);
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if (ret)
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return ret;
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ctrl->ctrl_config |= NVME_CC_ENABLE;
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ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
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if (ret)
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return ret;
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@ -3453,6 +3453,8 @@ static const struct pci_device_id nvme_id_table[] = {
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.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
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{ PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
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.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
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{ PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
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.driver_data = NVME_QUIRK_BOGUS_NID, },
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{ PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
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.driver_data = NVME_QUIRK_BOGUS_NID, },
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{ PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
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@ -97,7 +97,7 @@ static u16 nvmet_passthru_override_id_ctrl(struct nvmet_req *req)
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id->sgls |= cpu_to_le32(1 << 20);
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/*
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* When passsthru controller is setup using nvme-loop transport it will
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* When passthru controller is setup using nvme-loop transport it will
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* export the passthru ctrl subsysnqn (PCIe NVMe ctrl) and will fail in
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* the nvme/host/core.c in the nvme_init_subsystem()->nvme_active_ctrl()
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* code path with duplicate ctr subsynqn. In order to prevent that we
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