powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS boards
- Update the device tree per QE USB bindings; - Add timer (FSL GTM) node; - Add gpio-controller node for BCSR13 bank (GPIOs on that bank are used to control the USB transceiver); - Set up other BCSR registers; - Configure the QE Par IO. The work is loosely based on Li Yang's patch[1], which was used to support peripheral mode only. [1] http://ozlabs.org/pipermail/linuxppc-dev/2008-August/061357.html The s-o-b line of the original patch preserved here. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Anton Vorontsov
Kumar Gala
parent
3d64de9c50
commit
c9c5e52d44
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@ -69,8 +69,18 @@
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};
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bcsr@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8360mds-bcsr";
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reg = <1 0 0x8000>;
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ranges = <0 1 0 0x8000>;
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bcsr13: gpio-controller@d {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8360mds-bcsr-gpio";
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reg = <0xd 1>;
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gpio-controller;
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};
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};
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};
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@ -195,10 +205,21 @@
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};
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par_io@1400 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x1400 0x100>;
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ranges = <0 0x1400 0x100>;
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device_type = "par_io";
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num-ports = <7>;
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qe_pio_b: gpio-controller@18 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8360-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank";
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reg = <0x18 0x18>;
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gpio-controller;
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};
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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@ -282,6 +303,15 @@
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};
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};
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timer@440 {
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compatible = "fsl,mpc8360-qe-gtm",
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"fsl,qe-gtm", "fsl,gtm";
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reg = <0x440 0x40>;
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clock-frequency = <132000000>;
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interrupts = <12 13 14 15>;
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interrupt-parent = <&qeic>;
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};
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spi@4c0 {
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cell-index = <0>;
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compatible = "fsl,spi";
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@ -301,11 +331,20 @@
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};
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usb@6c0 {
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compatible = "qe_udc";
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compatible = "fsl,mpc8360-qe-usb",
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"fsl,mpc8323-qe-usb";
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reg = <0x6c0 0x40 0x8b00 0x100>;
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interrupts = <11>;
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interrupt-parent = <&qeic>;
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mode = "slave";
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fsl,fullspeed-clock = "clk21";
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fsl,lowspeed-clock = "brg9";
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gpios = <&qe_pio_b 2 0 /* USBOE */
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&qe_pio_b 3 0 /* USBTP */
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&qe_pio_b 8 0 /* USBTN */
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&qe_pio_b 9 0 /* USBRP */
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&qe_pio_b 11 0 /* USBRN */
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&bcsr13 5 0 /* SPEED */
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&bcsr13 4 1>; /* POWER */
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};
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enet0: ucc@2000 {
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@ -44,6 +44,7 @@
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <sysdev/simple_gpio.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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@ -93,6 +94,16 @@ static void __init mpc836x_mds_setup_arch(void)
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for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
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par_io_of_config(np);
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#ifdef CONFIG_QE_USB
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/* Must fixup Par IO before QE GPIO chips are registered. */
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par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
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par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
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par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
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par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
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par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
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par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
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par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
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#endif /* CONFIG_QE_USB */
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}
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if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
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@ -151,6 +162,70 @@ static int __init mpc836x_declare_of_platform_devices(void)
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}
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machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
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#ifdef CONFIG_QE_USB
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static int __init mpc836x_usb_cfg(void)
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{
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u8 __iomem *bcsr;
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struct device_node *np;
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const char *mode;
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int ret = 0;
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
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if (!np)
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return -ENODEV;
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bcsr = of_iomap(np, 0);
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of_node_put(np);
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if (!bcsr)
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return -ENOMEM;
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
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if (!np) {
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ret = -ENODEV;
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goto err;
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}
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#define BCSR8_TSEC1M_MASK (0x3 << 6)
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#define BCSR8_TSEC1M_RGMII (0x0 << 6)
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#define BCSR8_TSEC2M_MASK (0x3 << 4)
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#define BCSR8_TSEC2M_RGMII (0x0 << 4)
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/*
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* Default is GMII (2), but we should set it to RGMII (0) if we use
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* USB (Eth PHY is in RGMII mode anyway).
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*/
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clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
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BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
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#define BCSR13_USBMASK 0x0f
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#define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */
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#define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */
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#define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */
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#define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */
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clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
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mode = of_get_property(np, "mode", NULL);
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if (mode && !strcmp(mode, "peripheral")) {
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setbits8(&bcsr[13], BCSR13_nUSBVCC);
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qe_usb_clock_set(QE_CLK21, 48000000);
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} else {
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setbits8(&bcsr[13], BCSR13_USBMODE);
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/*
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* The BCSR GPIOs are used to control power and
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* speed of the USB transceiver. This is needed for
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* the USB Host only.
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*/
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simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
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}
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of_node_put(np);
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err:
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iounmap(bcsr);
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return ret;
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}
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machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
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#endif /* CONFIG_QE_USB */
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static void __init mpc836x_mds_init_IRQ(void)
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{
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struct device_node *np;
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