Renesas DRM/KMS drivers:
- Group drivers in renesas subdirectory to prepare for new platform - Drop deprecated R-Car H3 ES1.x support -----BEGIN PGP SIGNATURE----- iJgEABYKAEAWIQTAnvhxs4J7QT+XHKnMPy2AAyfeZAUCZHTLBCIcbGF1cmVudC5w aW5jaGFydEBpZGVhc29uYm9hcmQuY29tAAoJEMw/LYADJ95kCXwA/38vhjJ86Yx9 dZy4Asay1gOIq/C43PSMqQxh1V7hTPvrAQCM0CN2AA/iqjBthYdzz20Usk31xeN+ BaAGl+J61H+jAg== =CC+6 -----END PGP SIGNATURE----- Merge tag 'drm-next-20230529' of git://git.kernel.org/pub/scm/linux/kernel/git/pinchartl/linux into drm-next Renesas DRM/KMS drivers: - Group drivers in renesas subdirectory to prepare for new platform - Drop deprecated R-Car H3 ES1.x support Signed-off-by: Dave Airlie <airlied@redhat.com> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230602111504.GA24855@pendragon.ideasonboard.com
This commit is contained in:
Dave Airlie
commit
c9b685df2d
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@ -6981,8 +6981,7 @@ F: Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
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F: Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
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F: Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
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F: Documentation/devicetree/bindings/display/renesas,du.yaml
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F: drivers/gpu/drm/rcar-du/
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F: drivers/gpu/drm/shmobile/
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F: drivers/gpu/drm/renesas/
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F: include/linux/platform_data/shmob_drm.h
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DRM DRIVERS FOR ROCKCHIP
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@ -289,9 +289,7 @@ source "drivers/gpu/drm/armada/Kconfig"
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source "drivers/gpu/drm/atmel-hlcdc/Kconfig"
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source "drivers/gpu/drm/rcar-du/Kconfig"
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source "drivers/gpu/drm/shmobile/Kconfig"
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source "drivers/gpu/drm/renesas/Kconfig"
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source "drivers/gpu/drm/sun4i/Kconfig"
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@ -156,8 +156,7 @@ obj-$(CONFIG_DRM_UDL) += udl/
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obj-$(CONFIG_DRM_AST) += ast/
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obj-$(CONFIG_DRM_ARMADA) += armada/
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obj-$(CONFIG_DRM_ATMEL_HLCDC) += atmel-hlcdc/
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obj-y += rcar-du/
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obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
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obj-y += renesas/
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obj-y += omapdrm/
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obj-$(CONFIG_DRM_SUN4I) += sun4i/
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obj-y += tilcdc/
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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source "drivers/gpu/drm/renesas/rcar-du/Kconfig"
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source "drivers/gpu/drm/renesas/shmobile/Kconfig"
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += rcar-du/
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obj-$(CONFIG_DRM_SHMOBILE) += shmobile/
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@ -223,20 +223,6 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
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* DU channels that have a display PLL can't use the internal
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* system clock, and have no internal clock divider.
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*/
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/*
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* The H3 ES1.x exhibits dot clock duty cycle stability issues.
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* We can work around them by configuring the DPLL to twice the
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* desired frequency, coupled with a /2 post-divider. Restrict
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* the workaround to H3 ES1.x as ES2.0 and all other SoCs have
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* no post-divider when a display PLL is present (as shown by
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* the workaround breaking HDMI output on M3-W during testing).
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*/
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if (rcdu->info->quirks & RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY) {
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target *= 2;
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div = 1;
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}
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extclk = clk_get_rate(rcrtc->extclock);
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rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
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@ -245,30 +231,13 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
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| DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
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| DPLLCR_STBY;
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if (rcrtc->index == 1) {
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if (rcrtc->index == 1)
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dpllcr |= DPLLCR_PLCS1
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| DPLLCR_INCS_DOTCLKIN1;
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} else {
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dpllcr |= DPLLCR_PLCS0_PLL
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else
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dpllcr |= DPLLCR_PLCS0
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| DPLLCR_INCS_DOTCLKIN0;
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/*
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* On ES2.x we have a single mux controlled via bit 21,
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* which selects between DCLKIN source (bit 21 = 0) and
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* a PLL source (bit 21 = 1), where the PLL is always
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* PLL1.
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*
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* On ES1.x we have an additional mux, controlled
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* via bit 20, for choosing between PLL0 (bit 20 = 0)
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* and PLL1 (bit 20 = 1). We always want to use PLL1,
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* so on ES1.x, in addition to setting bit 21, we need
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* to set the bit 20.
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*/
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if (rcdu->info->quirks & RCAR_DU_QUIRK_H3_ES1_PLL)
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dpllcr |= DPLLCR_PLCS0_H3ES1X_PLL1;
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}
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rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
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escr = ESCR_DCLKSEL_DCLKIN | div;
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@ -16,7 +16,6 @@
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <linux/wait.h>
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#include <drm/drm_atomic_helper.h>
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@ -387,43 +386,6 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
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.dpll_mask = BIT(2) | BIT(1),
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};
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static const struct rcar_du_device_info rcar_du_r8a7795_es1_info = {
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.gen = 3,
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.features = RCAR_DU_FEATURE_CRTC_IRQ
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| RCAR_DU_FEATURE_CRTC_CLOCK
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| RCAR_DU_FEATURE_VSP1_SOURCE
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| RCAR_DU_FEATURE_INTERLACED
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| RCAR_DU_FEATURE_TVM_SYNC,
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.quirks = RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY
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| RCAR_DU_QUIRK_H3_ES1_PLL,
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.channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
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.routes = {
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/*
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* R8A7795 has one RGB output, two HDMI outputs and one
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* LVDS output.
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*/
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[RCAR_DU_OUTPUT_DPAD0] = {
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.possible_crtcs = BIT(3),
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.port = 0,
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},
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[RCAR_DU_OUTPUT_HDMI0] = {
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.possible_crtcs = BIT(1),
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.port = 1,
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},
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[RCAR_DU_OUTPUT_HDMI1] = {
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.possible_crtcs = BIT(2),
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.port = 2,
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},
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[RCAR_DU_OUTPUT_LVDS0] = {
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.possible_crtcs = BIT(0),
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.port = 3,
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},
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},
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.num_lvds = 1,
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.num_rpf = 5,
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.dpll_mask = BIT(2) | BIT(1),
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};
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static const struct rcar_du_device_info rcar_du_r8a7796_info = {
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.gen = 3,
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.features = RCAR_DU_FEATURE_CRTC_IRQ
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@ -614,11 +576,6 @@ static const struct of_device_id rcar_du_of_table[] = {
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MODULE_DEVICE_TABLE(of, rcar_du_of_table);
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static const struct soc_device_attribute rcar_du_soc_table[] = {
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{ .soc_id = "r8a7795", .revision = "ES1.*", .data = &rcar_du_r8a7795_es1_info },
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{ /* sentinel */ }
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};
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const char *rcar_du_output_name(enum rcar_du_output output)
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{
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static const char * const names[] = {
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@ -707,7 +664,6 @@ static void rcar_du_shutdown(struct platform_device *pdev)
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static int rcar_du_probe(struct platform_device *pdev)
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{
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const struct soc_device_attribute *soc_attr;
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struct rcar_du_device *rcdu;
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unsigned int mask;
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int ret;
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@ -725,10 +681,6 @@ static int rcar_du_probe(struct platform_device *pdev)
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rcdu->info = of_device_get_match_data(rcdu->dev);
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soc_attr = soc_device_match(rcar_du_soc_table);
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if (soc_attr)
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rcdu->info = soc_attr->data;
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platform_set_drvdata(pdev, rcdu);
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/* I/O resources */
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@ -34,8 +34,6 @@ struct rcar_du_device;
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#define RCAR_DU_FEATURE_NO_BLENDING BIT(5) /* PnMR.SPIM does not have ALP nor EOR bits */
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#define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */
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#define RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY BIT(1) /* H3 ES1 has pclk stability issue */
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#define RCAR_DU_QUIRK_H3_ES1_PLL BIT(2) /* H3 ES1 PLL setup differs from non-ES1 */
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enum rcar_du_output {
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RCAR_DU_OUTPUT_DPAD0,
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@ -283,8 +283,7 @@
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#define DPLLCR 0x20044
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#define DPLLCR_CODE (0x95 << 24)
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#define DPLLCR_PLCS1 (1 << 23)
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#define DPLLCR_PLCS0_PLL (1 << 21)
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#define DPLLCR_PLCS0_H3ES1X_PLL1 (1 << 20)
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#define DPLLCR_PLCS0 (1 << 21)
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#define DPLLCR_CLKE (1 << 18)
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#define DPLLCR_FDPLL(n) ((n) << 12)
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#define DPLLCR_N(n) ((n) << 5)
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