phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct
As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Manivannan Sadhasivam
Vinod Koul
parent
fcfcae3b75
commit
c9a7b0ddb5
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@ -532,21 +532,26 @@ struct qmp_ufs_offsets {
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u16 rx2;
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};
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struct qmp_phy_cfg_tbls {
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/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
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const struct qmp_phy_init_tbl *serdes;
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int serdes_num;
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const struct qmp_phy_init_tbl *tx;
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int tx_num;
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const struct qmp_phy_init_tbl *rx;
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int rx_num;
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const struct qmp_phy_init_tbl *pcs;
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int pcs_num;
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};
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/* struct qmp_phy_cfg - per-PHY initialization config */
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struct qmp_phy_cfg {
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int lanes;
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const struct qmp_ufs_offsets *offsets;
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/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
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const struct qmp_phy_init_tbl *serdes_tbl;
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int serdes_tbl_num;
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const struct qmp_phy_init_tbl *tx_tbl;
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int tx_tbl_num;
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const struct qmp_phy_init_tbl *rx_tbl;
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int rx_tbl_num;
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const struct qmp_phy_init_tbl *pcs_tbl;
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int pcs_tbl_num;
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/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
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const struct qmp_phy_cfg_tbls tbls;
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/* clock ids to be requested */
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const char * const *clk_list;
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@ -637,12 +642,14 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
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static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
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.lanes = 1,
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.serdes_tbl = msm8996_ufsphy_serdes,
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.serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
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.tx_tbl = msm8996_ufsphy_tx,
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.tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx),
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.rx_tbl = msm8996_ufsphy_rx,
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.rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx),
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.tbls = {
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.serdes = msm8996_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
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.tx = msm8996_ufsphy_tx,
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.tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
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.rx = msm8996_ufsphy_rx,
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.rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
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},
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.clk_list = msm8996_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
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@ -660,14 +667,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
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.offsets = &qmp_ufs_offsets_v5,
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.serdes_tbl = sm8350_ufsphy_serdes,
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.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
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.tx_tbl = sm8350_ufsphy_tx,
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.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
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.rx_tbl = sm8350_ufsphy_rx,
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.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
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.pcs_tbl = sm8350_ufsphy_pcs,
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.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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.tbls = {
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.serdes = sm8350_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
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.tx = sm8350_ufsphy_tx,
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.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
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.rx = sm8350_ufsphy_rx,
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.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
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.pcs = sm8350_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -678,14 +687,16 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
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static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
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.lanes = 2,
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.serdes_tbl = sdm845_ufsphy_serdes,
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.serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
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.tx_tbl = sdm845_ufsphy_tx,
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.tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx),
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.rx_tbl = sdm845_ufsphy_rx,
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.rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx),
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.pcs_tbl = sdm845_ufsphy_pcs,
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.pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
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.tbls = {
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.serdes = sdm845_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
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.tx = sdm845_ufsphy_tx,
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.tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
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.rx = sdm845_ufsphy_rx,
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.rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
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.pcs = sdm845_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -700,14 +711,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
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.offsets = &qmp_ufs_offsets_v5,
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.serdes_tbl = sm6115_ufsphy_serdes,
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.serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
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.tx_tbl = sm6115_ufsphy_tx,
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.tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx),
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.rx_tbl = sm6115_ufsphy_rx,
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.rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx),
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.pcs_tbl = sm6115_ufsphy_pcs,
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.pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
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.tbls = {
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.serdes = sm6115_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
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.tx = sm6115_ufsphy_tx,
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.tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
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.rx = sm6115_ufsphy_rx,
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.rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
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.pcs = sm6115_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -720,14 +733,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
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static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
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.lanes = 2,
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.serdes_tbl = sm8150_ufsphy_serdes,
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.serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
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.tx_tbl = sm8150_ufsphy_tx,
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.tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx),
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.rx_tbl = sm8150_ufsphy_rx,
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.rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx),
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.pcs_tbl = sm8150_ufsphy_pcs,
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.pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
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.tbls = {
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.serdes = sm8150_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
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.tx = sm8150_ufsphy_tx,
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.tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
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.rx = sm8150_ufsphy_rx,
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.rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
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.pcs = sm8150_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -738,14 +753,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
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static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
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.lanes = 2,
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.serdes_tbl = sm8350_ufsphy_serdes,
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.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
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.tx_tbl = sm8350_ufsphy_tx,
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.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
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.rx_tbl = sm8350_ufsphy_rx,
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.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
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.pcs_tbl = sm8350_ufsphy_pcs,
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.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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.tbls = {
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.serdes = sm8350_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
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.tx = sm8350_ufsphy_tx,
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.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
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.rx = sm8350_ufsphy_rx,
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.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
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.pcs = sm8350_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -756,14 +773,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
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static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
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.lanes = 2,
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.serdes_tbl = sm8350_ufsphy_serdes,
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.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
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.tx_tbl = sm8350_ufsphy_tx,
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.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
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.rx_tbl = sm8350_ufsphy_rx,
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.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
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.pcs_tbl = sm8350_ufsphy_pcs,
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.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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.tbls = {
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.serdes = sm8350_ufsphy_serdes,
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.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
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.tx = sm8350_ufsphy_tx,
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.tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
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.rx = sm8350_ufsphy_rx,
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.rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
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.pcs = sm8350_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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},
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.clk_list = sm8450_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -797,16 +816,40 @@ static void qmp_ufs_configure(void __iomem *base,
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qmp_ufs_configure_lane(base, tbl, num, 0xff);
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}
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static int qmp_ufs_serdes_init(struct qmp_ufs *qmp)
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static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
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{
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void __iomem *serdes = qmp->serdes;
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qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
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}
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static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
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{
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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void __iomem *serdes = qmp->serdes;
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const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
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int serdes_tbl_num = cfg->serdes_tbl_num;
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void __iomem *tx = qmp->tx;
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void __iomem *rx = qmp->rx;
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qmp_ufs_configure(serdes, serdes_tbl, serdes_tbl_num);
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qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
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qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
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return 0;
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if (cfg->lanes >= 2) {
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qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
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qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
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}
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}
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static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
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{
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void __iomem *pcs = qmp->pcs;
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qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
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}
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static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
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{
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qmp_ufs_serdes_init(qmp, &cfg->tbls);
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qmp_ufs_lanes_init(qmp, &cfg->tbls);
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qmp_ufs_pcs_init(qmp, &cfg->tbls);
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}
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static int qmp_ufs_com_init(struct qmp_ufs *qmp)
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@ -893,25 +936,12 @@ static int qmp_ufs_power_on(struct phy *phy)
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{
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struct qmp_ufs *qmp = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qmp->cfg;
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void __iomem *tx = qmp->tx;
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void __iomem *rx = qmp->rx;
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void __iomem *pcs = qmp->pcs;
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void __iomem *status;
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unsigned int val;
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int ret;
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qmp_ufs_serdes_init(qmp);
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/* Tx, Rx, and PCS configurations */
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qmp_ufs_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
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qmp_ufs_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
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if (cfg->lanes >= 2) {
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qmp_ufs_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
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qmp_ufs_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
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}
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qmp_ufs_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
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qmp_ufs_init_registers(qmp, cfg);
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ret = reset_control_deassert(qmp->ufs_reset);
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if (ret)
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