drm/amd/powerplay: revise calling chain on setting soft limit
This helps to maintain clear code layers and drop unnecessary parameter. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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661b94f5ac
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c98f31d17c
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@ -1464,7 +1464,9 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val)
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ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq, true);
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if (ret || val > max_freq || val < min_freq)
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return -EINVAL;
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ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val, true);
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ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val);
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} else {
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return 0;
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}
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pm_runtime_mark_last_busy(adev->ddev->dev);
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@ -238,18 +238,24 @@ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t
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return ret;
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}
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int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
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uint32_t min, uint32_t max, bool lock_needed)
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int smu_set_soft_freq_range(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t min,
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uint32_t max)
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{
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int ret = 0;
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if (!smu_clk_dpm_is_enabled(smu, clk_type))
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return 0;
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if (lock_needed)
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mutex_lock(&smu->mutex);
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ret = smu_set_soft_freq_limited_range(smu, clk_type, min, max);
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if (lock_needed)
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if (smu->ppt_funcs->set_soft_freq_limited_range)
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ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
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clk_type,
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min,
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max);
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mutex_unlock(&smu->mutex);
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return ret;
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@ -722,7 +722,7 @@ int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
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int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
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uint32_t *min, uint32_t *max, bool lock_needed);
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int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
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uint32_t min, uint32_t max, bool lock_needed);
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uint32_t min, uint32_t max);
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int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
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uint32_t *min_value, uint32_t *max_value);
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enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
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@ -1066,7 +1066,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,
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if (ret)
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return size;
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ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
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if (ret)
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return size;
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break;
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@ -1190,7 +1190,7 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
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return ret;
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force_freq = highest ? max_freq : min_freq;
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ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
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if (ret)
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return ret;
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}
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@ -1216,7 +1216,7 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu)
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
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if (ret)
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return ret;
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}
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@ -1772,10 +1772,10 @@ static int navi10_set_standard_performance_level(struct smu_context *smu)
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return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
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}
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ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
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if (ret)
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return ret;
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@ -1840,10 +1840,10 @@ static int navi10_set_peak_performance_level(struct smu_context *smu)
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
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if (ret)
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return ret;
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@ -439,7 +439,7 @@ static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
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return ret;
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force_freq = highest ? max_freq : min_freq;
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ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
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ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
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if (ret)
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return ret;
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}
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@ -472,7 +472,7 @@ static int renoir_unforce_dpm_levels(struct smu_context *smu) {
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
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ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
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if (ret)
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return ret;
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}
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@ -720,7 +720,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
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ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
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if (ret)
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return ret;
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@ -728,7 +728,7 @@ static int renoir_set_peak_clock_by_device(struct smu_context *smu)
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
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ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
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if (ret)
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return ret;
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@ -858,6 +858,22 @@ print_clk_out:
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return size;
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}
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int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t min, uint32_t max)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret;
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if (clk_type == SMU_GFXCLK)
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amdgpu_gfx_off_ctrl(adev, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
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if (clk_type == SMU_GFXCLK)
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amdgpu_gfx_off_ctrl(adev, true);
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return ret;
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}
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static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type, uint32_t mask)
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{
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@ -893,7 +909,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
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if (ret)
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goto forec_level_out;
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ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
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ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
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if (ret)
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goto forec_level_out;
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break;
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@ -991,7 +1007,7 @@ static int sienna_cichlid_force_dpm_limit_value(struct smu_context *smu, bool hi
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return ret;
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force_freq = highest ? max_freq : min_freq;
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ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq, false);
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ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
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if (ret)
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return ret;
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}
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@ -1017,7 +1033,7 @@ static int sienna_cichlid_unforce_dpm_levels(struct smu_context *smu)
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq, false);
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ret = sienna_cichlid_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
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if (ret)
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return ret;
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}
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@ -1568,10 +1584,10 @@ static int sienna_cichlid_set_standard_performance_level(struct smu_context *smu
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return sienna_cichlid_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
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}
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ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq, false);
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ret = sienna_cichlid_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
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if (ret)
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return ret;
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ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq, false);
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ret = sienna_cichlid_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
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if (ret)
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return ret;
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@ -1751,22 +1767,6 @@ static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
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return ret;
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}
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static int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t min, uint32_t max)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret;
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if (clk_type == SMU_GFXCLK)
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amdgpu_gfx_off_ctrl(adev, false);
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ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min, max);
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if (clk_type == SMU_GFXCLK)
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amdgpu_gfx_off_ctrl(adev, true);
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return ret;
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}
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static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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