drm/i915/selftests: Try to detect rollback during batchbuffer preemption
Since batch buffers dominant execution time, most preemption requests should naturally occur during execution of a batch buffer. We wish to verify that should a preemption occur within a batch buffer, when we come to restart that batch buffer, it occurs at the interrupted instruction and most importantly does not rollback to an earlier point. v2: Do not clear the GPR at the start of the batch, but rely on them being clear for new contexts. Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200422100903.25216-1-chris@chris-wilson.co.uk
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@ -21,7 +21,8 @@
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#include "gem/selftests/mock_context.h"
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#define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
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#define NUM_GPR_DW (16 * 2) /* each GPR is 2 dwords */
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#define NUM_GPR 16
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#define NUM_GPR_DW (NUM_GPR * 2) /* each GPR is 2 dwords */
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static struct i915_vma *create_scratch(struct intel_gt *gt)
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{
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@ -2791,6 +2792,331 @@ static int live_preempt_gang(void *arg)
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return 0;
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}
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static struct i915_vma *
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create_gpr_user(struct intel_engine_cs *engine,
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struct i915_vma *result,
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unsigned int offset)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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u32 *cs;
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int err;
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int i;
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obj = i915_gem_object_create_internal(engine->i915, 4096);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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vma = i915_vma_instance(obj, result->vm, NULL);
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if (IS_ERR(vma)) {
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i915_gem_object_put(obj);
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return vma;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err) {
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i915_vma_put(vma);
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return ERR_PTR(err);
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}
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cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
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if (IS_ERR(cs)) {
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i915_vma_put(vma);
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return ERR_CAST(cs);
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}
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/* All GPR are clear for new contexts. We use GPR(0) as a constant */
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*cs++ = MI_LOAD_REGISTER_IMM(1);
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*cs++ = CS_GPR(engine, 0);
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*cs++ = 1;
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for (i = 1; i < NUM_GPR; i++) {
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u64 addr;
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/*
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* Perform: GPR[i]++
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*
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* As we read and write into the context saved GPR[i], if
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* we restart this batch buffer from an earlier point, we
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* will repeat the increment and store a value > 1.
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*/
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*cs++ = MI_MATH(4);
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*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(i));
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*cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(0));
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*cs++ = MI_MATH_ADD;
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*cs++ = MI_MATH_STORE(MI_MATH_REG(i), MI_MATH_REG_ACCU);
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addr = result->node.start + offset + i * sizeof(*cs);
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*cs++ = MI_STORE_REGISTER_MEM_GEN8;
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*cs++ = CS_GPR(engine, 2 * i);
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*cs++ = lower_32_bits(addr);
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*cs++ = upper_32_bits(addr);
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*cs++ = MI_SEMAPHORE_WAIT |
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MI_SEMAPHORE_POLL |
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MI_SEMAPHORE_SAD_GTE_SDD;
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*cs++ = i;
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*cs++ = lower_32_bits(result->node.start);
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*cs++ = upper_32_bits(result->node.start);
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}
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*cs++ = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(obj);
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i915_gem_object_unpin_map(obj);
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return vma;
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}
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static struct i915_vma *create_global(struct intel_gt *gt, size_t sz)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int err;
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obj = i915_gem_object_create_internal(gt->i915, sz);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
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if (IS_ERR(vma)) {
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i915_gem_object_put(obj);
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return vma;
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}
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err = i915_ggtt_pin(vma, 0, 0);
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if (err) {
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i915_vma_put(vma);
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return ERR_PTR(err);
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}
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return vma;
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}
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static struct i915_request *
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create_gpr_client(struct intel_engine_cs *engine,
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struct i915_vma *global,
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unsigned int offset)
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{
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struct i915_vma *batch, *vma;
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struct intel_context *ce;
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struct i915_request *rq;
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int err;
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ce = intel_context_create(engine);
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if (IS_ERR(ce))
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return ERR_CAST(ce);
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vma = i915_vma_instance(global->obj, ce->vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto out_ce;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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goto out_ce;
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batch = create_gpr_user(engine, vma, offset);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_vma;
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}
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_batch;
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}
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i915_vma_lock(vma);
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err = i915_request_await_object(rq, vma->obj, false);
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if (!err)
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err = i915_vma_move_to_active(vma, rq, 0);
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i915_vma_unlock(vma);
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i915_vma_lock(batch);
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if (!err)
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err = i915_request_await_object(rq, batch->obj, false);
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if (!err)
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err = i915_vma_move_to_active(batch, rq, 0);
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if (!err)
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err = rq->engine->emit_bb_start(rq,
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batch->node.start,
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PAGE_SIZE, 0);
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i915_vma_unlock(batch);
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i915_vma_unpin(batch);
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if (!err)
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i915_request_get(rq);
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i915_request_add(rq);
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out_batch:
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i915_vma_put(batch);
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out_vma:
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i915_vma_unpin(vma);
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out_ce:
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intel_context_put(ce);
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return err ? ERR_PTR(err) : rq;
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}
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static int preempt_user(struct intel_engine_cs *engine,
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struct i915_vma *global,
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int id)
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{
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struct i915_sched_attr attr = {
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.priority = I915_PRIORITY_MAX
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};
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struct i915_request *rq;
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int err = 0;
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u32 *cs;
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rq = intel_engine_create_kernel_request(engine);
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if (IS_ERR(rq))
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return PTR_ERR(rq);
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs)) {
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i915_request_add(rq);
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return PTR_ERR(cs);
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}
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*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
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*cs++ = i915_ggtt_offset(global);
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*cs++ = 0;
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*cs++ = id;
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intel_ring_advance(rq, cs);
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i915_request_get(rq);
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i915_request_add(rq);
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engine->schedule(rq, &attr);
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if (i915_request_wait(rq, 0, HZ / 2) < 0)
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err = -ETIME;
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i915_request_put(rq);
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return err;
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}
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static int live_preempt_user(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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struct i915_vma *global;
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enum intel_engine_id id;
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u32 *result;
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int err = 0;
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if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
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return 0;
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/*
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* In our other tests, we look at preemption in carefully
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* controlled conditions in the ringbuffer. Since most of the
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* time is spent in user batches, most of our preemptions naturally
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* occur there. We want to verify that when we preempt inside a batch
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* we continue on from the current instruction and do not roll back
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* to the start, or another earlier arbitration point.
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*
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* To verify this, we create a batch which is a mixture of
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* MI_MATH (gpr++) MI_SRM (gpr) and preemption points. Then with
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* a few preempting contexts thrown into the mix, we look for any
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* repeated instructions (which show up as incorrect values).
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*/
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global = create_global(gt, 4096);
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if (IS_ERR(global))
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return PTR_ERR(global);
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result = i915_gem_object_pin_map(global->obj, I915_MAP_WC);
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if (IS_ERR(result)) {
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i915_vma_unpin_and_release(&global, 0);
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return PTR_ERR(result);
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}
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for_each_engine(engine, gt, id) {
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struct i915_request *client[3] = {};
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struct igt_live_test t;
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int i;
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if (!intel_engine_has_preemption(engine))
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continue;
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if (IS_GEN(gt->i915, 8) && engine->class != RENDER_CLASS)
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continue; /* we need per-context GPR */
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if (igt_live_test_begin(&t, gt->i915, __func__, engine->name)) {
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err = -EIO;
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break;
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}
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memset(result, 0, 4096);
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for (i = 0; i < ARRAY_SIZE(client); i++) {
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struct i915_request *rq;
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rq = create_gpr_client(engine, global,
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NUM_GPR * i * sizeof(u32));
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if (IS_ERR(rq))
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goto end_test;
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client[i] = rq;
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}
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/* Continuously preempt the set of 3 running contexts */
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for (i = 1; i <= NUM_GPR; i++) {
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err = preempt_user(engine, global, i);
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if (err)
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goto end_test;
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}
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if (READ_ONCE(result[0]) != NUM_GPR) {
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pr_err("%s: Failed to release semaphore\n",
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engine->name);
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err = -EIO;
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goto end_test;
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}
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for (i = 0; i < ARRAY_SIZE(client); i++) {
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int gpr;
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if (i915_request_wait(client[i], 0, HZ / 2) < 0) {
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err = -ETIME;
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goto end_test;
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}
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for (gpr = 1; gpr < NUM_GPR; gpr++) {
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if (result[NUM_GPR * i + gpr] != 1) {
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pr_err("%s: Invalid result, client %d, gpr %d, result: %d\n",
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engine->name,
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i, gpr, result[NUM_GPR * i + gpr]);
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err = -EINVAL;
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goto end_test;
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}
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}
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}
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end_test:
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for (i = 0; i < ARRAY_SIZE(client); i++) {
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if (!client[i])
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break;
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i915_request_put(client[i]);
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}
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/* Flush the semaphores on error */
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smp_store_mb(result[0], -1);
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if (igt_live_test_end(&t))
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err = -EIO;
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if (err)
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break;
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}
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i915_vma_unpin_and_release(&global, I915_VMA_RELEASE_MAP);
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return err;
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}
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static int live_preempt_timeout(void *arg)
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{
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struct intel_gt *gt = arg;
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@ -3998,6 +4324,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
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SUBTEST(live_chain_preempt),
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SUBTEST(live_preempt_gang),
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SUBTEST(live_preempt_timeout),
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SUBTEST(live_preempt_user),
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SUBTEST(live_preempt_smoke),
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SUBTEST(live_virtual_engine),
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SUBTEST(live_virtual_mask),
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