Merge tag 'amd-drm-fixes-6.4-2023-06-14' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.4-2023-06-14: amdgpu: - GFX9 preemption fixes - Add missing radeon secondary PCI ID - vblflash fixes - SMU 13 fix - VCN 4.0 fix - Re-enable TOPDOWN flag for large BAR systems to fix regression - eDP fix - PSR hang fix - DPIA fix radeon: - fbdev client warning fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230615024011.7773-1-alexander.deucher@amd.com
This commit is contained in:
commit
c8ac109e21
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@ -1615,6 +1615,7 @@ static const u16 amdgpu_unsupported_pciidlist[] = {
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0x5874,
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0x5940,
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0x5941,
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0x5b70,
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0x5b72,
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0x5b73,
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0x5b74,
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@ -140,7 +140,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
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if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
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places[c].lpfn = visible_pfn;
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else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size)
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else
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places[c].flags |= TTM_PL_FLAG_TOPDOWN;
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if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
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@ -3548,6 +3548,9 @@ static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
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void *fw_pri_cpu_addr;
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int ret;
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if (adev->psp.vbflash_image_size == 0)
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return -EINVAL;
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dev_info(adev->dev, "VBIOS flash to PSP started");
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ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
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@ -3599,13 +3602,13 @@ static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
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}
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static const struct bin_attribute psp_vbflash_bin_attr = {
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.attr = {.name = "psp_vbflash", .mode = 0664},
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.attr = {.name = "psp_vbflash", .mode = 0660},
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.size = 0,
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.write = amdgpu_psp_vbflash_write,
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.read = amdgpu_psp_vbflash_read,
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};
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static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
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static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
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int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
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{
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@ -581,3 +581,21 @@ void amdgpu_ring_ib_end(struct amdgpu_ring *ring)
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if (ring->is_sw_ring)
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amdgpu_sw_ring_ib_end(ring);
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}
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void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring)
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{
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if (ring->is_sw_ring)
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amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CONTROL);
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}
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void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring)
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{
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if (ring->is_sw_ring)
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amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_CE);
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}
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void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring)
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{
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if (ring->is_sw_ring)
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amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE);
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}
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@ -227,6 +227,9 @@ struct amdgpu_ring_funcs {
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int (*preempt_ib)(struct amdgpu_ring *ring);
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void (*emit_mem_sync)(struct amdgpu_ring *ring);
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void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
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void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset);
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void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset);
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void (*patch_de)(struct amdgpu_ring *ring, unsigned offset);
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};
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struct amdgpu_ring {
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@ -318,10 +321,16 @@ struct amdgpu_ring {
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#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
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#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
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#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
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#define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
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#define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
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#define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))
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int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
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void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
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void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
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void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring);
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void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring);
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void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring);
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void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
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void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
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@ -105,6 +105,16 @@ static void amdgpu_mux_resubmit_chunks(struct amdgpu_ring_mux *mux)
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amdgpu_fence_update_start_timestamp(e->ring,
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chunk->sync_seq,
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ktime_get());
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if (chunk->sync_seq ==
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le32_to_cpu(*(e->ring->fence_drv.cpu_addr + 2))) {
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if (chunk->cntl_offset <= e->ring->buf_mask)
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amdgpu_ring_patch_cntl(e->ring,
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chunk->cntl_offset);
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if (chunk->ce_offset <= e->ring->buf_mask)
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amdgpu_ring_patch_ce(e->ring, chunk->ce_offset);
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if (chunk->de_offset <= e->ring->buf_mask)
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amdgpu_ring_patch_de(e->ring, chunk->de_offset);
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}
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amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, e->ring,
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chunk->start,
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chunk->end);
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@ -407,6 +417,17 @@ void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring)
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amdgpu_ring_mux_end_ib(mux, ring);
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}
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void amdgpu_sw_ring_ib_mark_offset(struct amdgpu_ring *ring, enum amdgpu_ring_mux_offset_type type)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_ring_mux *mux = &adev->gfx.muxer;
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unsigned offset;
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offset = ring->wptr & ring->buf_mask;
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amdgpu_ring_mux_ib_mark_offset(mux, ring, offset, type);
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}
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void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring)
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{
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struct amdgpu_mux_entry *e;
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@ -429,6 +450,10 @@ void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *r
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}
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chunk->start = ring->wptr;
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/* the initialized value used to check if they are set by the ib submission*/
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chunk->cntl_offset = ring->buf_mask + 1;
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chunk->de_offset = ring->buf_mask + 1;
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chunk->ce_offset = ring->buf_mask + 1;
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list_add_tail(&chunk->entry, &e->list);
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}
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@ -454,6 +479,41 @@ static void scan_and_remove_signaled_chunk(struct amdgpu_ring_mux *mux, struct a
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}
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}
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void amdgpu_ring_mux_ib_mark_offset(struct amdgpu_ring_mux *mux,
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struct amdgpu_ring *ring, u64 offset,
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enum amdgpu_ring_mux_offset_type type)
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{
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struct amdgpu_mux_entry *e;
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struct amdgpu_mux_chunk *chunk;
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e = amdgpu_ring_mux_sw_entry(mux, ring);
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if (!e) {
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DRM_ERROR("cannot find entry!\n");
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return;
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}
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chunk = list_last_entry(&e->list, struct amdgpu_mux_chunk, entry);
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if (!chunk) {
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DRM_ERROR("cannot find chunk!\n");
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return;
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}
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switch (type) {
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case AMDGPU_MUX_OFFSET_TYPE_CONTROL:
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chunk->cntl_offset = offset;
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break;
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case AMDGPU_MUX_OFFSET_TYPE_DE:
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chunk->de_offset = offset;
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break;
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case AMDGPU_MUX_OFFSET_TYPE_CE:
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chunk->ce_offset = offset;
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break;
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default:
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DRM_ERROR("invalid type (%d)\n", type);
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break;
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}
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}
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void amdgpu_ring_mux_end_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring)
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{
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struct amdgpu_mux_entry *e;
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@ -50,6 +50,12 @@ struct amdgpu_mux_entry {
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struct list_head list;
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};
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enum amdgpu_ring_mux_offset_type {
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AMDGPU_MUX_OFFSET_TYPE_CONTROL,
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AMDGPU_MUX_OFFSET_TYPE_DE,
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AMDGPU_MUX_OFFSET_TYPE_CE,
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};
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struct amdgpu_ring_mux {
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struct amdgpu_ring *real_ring;
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@ -72,12 +78,18 @@ struct amdgpu_ring_mux {
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* @sync_seq: the fence seqno related with the saved IB.
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* @start:- start location on the software ring.
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* @end:- end location on the software ring.
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* @control_offset:- the PRE_RESUME bit position used for resubmission.
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* @de_offset:- the anchor in write_data for de meta of resubmission.
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* @ce_offset:- the anchor in write_data for ce meta of resubmission.
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*/
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struct amdgpu_mux_chunk {
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struct list_head entry;
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uint32_t sync_seq;
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u64 start;
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u64 end;
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u64 cntl_offset;
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u64 de_offset;
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u64 ce_offset;
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};
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int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
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@ -89,6 +101,8 @@ u64 amdgpu_ring_mux_get_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ri
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u64 amdgpu_ring_mux_get_rptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
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void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
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void amdgpu_ring_mux_end_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring);
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void amdgpu_ring_mux_ib_mark_offset(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
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u64 offset, enum amdgpu_ring_mux_offset_type type);
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bool amdgpu_mcbp_handle_trailing_fence_irq(struct amdgpu_ring_mux *mux);
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u64 amdgpu_sw_ring_get_rptr_gfx(struct amdgpu_ring *ring);
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@ -97,6 +111,7 @@ void amdgpu_sw_ring_set_wptr_gfx(struct amdgpu_ring *ring);
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void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
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void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring);
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void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring);
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void amdgpu_sw_ring_ib_mark_offset(struct amdgpu_ring *ring, enum amdgpu_ring_mux_offset_type type);
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const char *amdgpu_sw_ring_name(int idx);
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unsigned int amdgpu_sw_ring_priority(int idx);
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@ -755,7 +755,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
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static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
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struct amdgpu_cu_info *cu_info);
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static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
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static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
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static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds);
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static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
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static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status);
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@ -5127,7 +5127,8 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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gfx_v9_0_ring_emit_de_meta(ring,
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(!amdgpu_sriov_vf(ring->adev) &&
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flags & AMDGPU_IB_PREEMPTED) ?
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true : false);
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true : false,
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job->gds_size > 0 && job->gds_base != 0);
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}
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amdgpu_ring_write(ring, header);
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@ -5138,9 +5139,83 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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#endif
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lower_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
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amdgpu_ring_ib_on_emit_cntl(ring);
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amdgpu_ring_write(ring, control);
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}
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static void gfx_v9_0_ring_patch_cntl(struct amdgpu_ring *ring,
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unsigned offset)
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{
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u32 control = ring->ring[offset];
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control |= INDIRECT_BUFFER_PRE_RESUME(1);
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ring->ring[offset] = control;
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}
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static void gfx_v9_0_ring_patch_ce_meta(struct amdgpu_ring *ring,
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unsigned offset)
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{
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struct amdgpu_device *adev = ring->adev;
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void *ce_payload_cpu_addr;
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uint64_t payload_offset, payload_size;
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payload_size = sizeof(struct v9_ce_ib_state);
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if (ring->is_mes_queue) {
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payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,
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gfx[0].gfx_meta_data) +
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offsetof(struct v9_gfx_meta_data, ce_payload);
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ce_payload_cpu_addr =
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amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);
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} else {
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payload_offset = offsetof(struct v9_gfx_meta_data, ce_payload);
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ce_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset;
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}
|
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|
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if (offset + (payload_size >> 2) <= ring->buf_mask + 1) {
|
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memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr, payload_size);
|
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} else {
|
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memcpy((void *)&ring->ring[offset], ce_payload_cpu_addr,
|
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(ring->buf_mask + 1 - offset) << 2);
|
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payload_size -= (ring->buf_mask + 1 - offset) << 2;
|
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memcpy((void *)&ring->ring[0],
|
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ce_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2),
|
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payload_size);
|
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}
|
||||
}
|
||||
|
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static void gfx_v9_0_ring_patch_de_meta(struct amdgpu_ring *ring,
|
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unsigned offset)
|
||||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
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void *de_payload_cpu_addr;
|
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uint64_t payload_offset, payload_size;
|
||||
|
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payload_size = sizeof(struct v9_de_ib_state);
|
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|
||||
if (ring->is_mes_queue) {
|
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payload_offset = offsetof(struct amdgpu_mes_ctx_meta_data,
|
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gfx[0].gfx_meta_data) +
|
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offsetof(struct v9_gfx_meta_data, de_payload);
|
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de_payload_cpu_addr =
|
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amdgpu_mes_ctx_get_offs_cpu_addr(ring, payload_offset);
|
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} else {
|
||||
payload_offset = offsetof(struct v9_gfx_meta_data, de_payload);
|
||||
de_payload_cpu_addr = adev->virt.csa_cpu_addr + payload_offset;
|
||||
}
|
||||
|
||||
if (offset + (payload_size >> 2) <= ring->buf_mask + 1) {
|
||||
memcpy((void *)&ring->ring[offset], de_payload_cpu_addr, payload_size);
|
||||
} else {
|
||||
memcpy((void *)&ring->ring[offset], de_payload_cpu_addr,
|
||||
(ring->buf_mask + 1 - offset) << 2);
|
||||
payload_size -= (ring->buf_mask + 1 - offset) << 2;
|
||||
memcpy((void *)&ring->ring[0],
|
||||
de_payload_cpu_addr + ((ring->buf_mask + 1 - offset) << 2),
|
||||
payload_size);
|
||||
}
|
||||
}
|
||||
|
||||
static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
|
||||
struct amdgpu_job *job,
|
||||
struct amdgpu_ib *ib,
|
||||
|
@ -5336,6 +5411,8 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
|
|||
amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
|
||||
|
||||
amdgpu_ring_ib_on_emit_ce(ring);
|
||||
|
||||
if (resume)
|
||||
amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
|
||||
sizeof(ce_payload) >> 2);
|
||||
|
@ -5369,10 +5446,6 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring)
|
|||
amdgpu_ring_alloc(ring, 13);
|
||||
gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
|
||||
ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT);
|
||||
/*reset the CP_VMID_PREEMPT after trailing fence*/
|
||||
amdgpu_ring_emit_wreg(ring,
|
||||
SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),
|
||||
0x0);
|
||||
|
||||
/* assert IB preemption, emit the trailing fence */
|
||||
kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
|
||||
|
@ -5395,6 +5468,10 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring)
|
|||
DRM_WARN("ring %d timeout to preempt ib\n", ring->idx);
|
||||
}
|
||||
|
||||
/*reset the CP_VMID_PREEMPT after trailing fence*/
|
||||
amdgpu_ring_emit_wreg(ring,
|
||||
SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),
|
||||
0x0);
|
||||
amdgpu_ring_commit(ring);
|
||||
|
||||
/* deassert preemption condition */
|
||||
|
@ -5402,7 +5479,7 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring)
|
|||
return r;
|
||||
}
|
||||
|
||||
static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
|
||||
static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume, bool usegds)
|
||||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
struct v9_de_ib_state de_payload = {0};
|
||||
|
@ -5433,8 +5510,10 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
|
|||
PAGE_SIZE);
|
||||
}
|
||||
|
||||
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
|
||||
de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
|
||||
if (usegds) {
|
||||
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
|
||||
de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
|
||||
}
|
||||
|
||||
cnt = (sizeof(de_payload) >> 2) + 4 - 2;
|
||||
amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
|
||||
|
@ -5445,6 +5524,7 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
|
|||
amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
|
||||
amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
|
||||
|
||||
amdgpu_ring_ib_on_emit_de(ring);
|
||||
if (resume)
|
||||
amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
|
||||
sizeof(de_payload) >> 2);
|
||||
|
@ -6855,6 +6935,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {
|
|||
.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
|
||||
.soft_recovery = gfx_v9_0_ring_soft_recovery,
|
||||
.emit_mem_sync = gfx_v9_0_emit_mem_sync,
|
||||
.patch_cntl = gfx_v9_0_ring_patch_cntl,
|
||||
.patch_de = gfx_v9_0_ring_patch_de_meta,
|
||||
.patch_ce = gfx_v9_0_ring_patch_ce_meta,
|
||||
};
|
||||
|
||||
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
|
||||
|
|
|
@ -129,7 +129,11 @@ static int vcn_v4_0_sw_init(void *handle)
|
|||
if (adev->vcn.harvest_config & (1 << i))
|
||||
continue;
|
||||
|
||||
atomic_set(&adev->vcn.inst[i].sched_score, 0);
|
||||
/* Init instance 0 sched_score to 1, so it's scheduled after other instances */
|
||||
if (i == 0)
|
||||
atomic_set(&adev->vcn.inst[i].sched_score, 1);
|
||||
else
|
||||
atomic_set(&adev->vcn.inst[i].sched_score, 0);
|
||||
|
||||
/* VCN UNIFIED TRAP */
|
||||
r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
|
||||
|
|
|
@ -7196,7 +7196,13 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
|
|||
drm_add_modes_noedid(connector, 1920, 1080);
|
||||
} else {
|
||||
amdgpu_dm_connector_ddc_get_modes(connector, edid);
|
||||
amdgpu_dm_connector_add_common_modes(encoder, connector);
|
||||
/* most eDP supports only timings from its edid,
|
||||
* usually only detailed timings are available
|
||||
* from eDP edid. timings which are not from edid
|
||||
* may damage eDP
|
||||
*/
|
||||
if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
|
||||
amdgpu_dm_connector_add_common_modes(encoder, connector);
|
||||
amdgpu_dm_connector_add_freesync_modes(connector, edid);
|
||||
}
|
||||
amdgpu_dm_fbc_init(connector);
|
||||
|
@ -8198,6 +8204,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
|
|||
if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
|
||||
bundle->stream_update.abm_level = &acrtc_state->abm_level;
|
||||
|
||||
mutex_lock(&dm->dc_lock);
|
||||
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
|
||||
acrtc_state->stream->link->psr_settings.psr_allow_active)
|
||||
amdgpu_dm_psr_disable(acrtc_state->stream);
|
||||
mutex_unlock(&dm->dc_lock);
|
||||
|
||||
/*
|
||||
* If FreeSync state on the stream has changed then we need to
|
||||
* re-adjust the min/max bounds now that DC doesn't handle this
|
||||
|
@ -8211,10 +8223,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
|
|||
spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
|
||||
}
|
||||
mutex_lock(&dm->dc_lock);
|
||||
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
|
||||
acrtc_state->stream->link->psr_settings.psr_allow_active)
|
||||
amdgpu_dm_psr_disable(acrtc_state->stream);
|
||||
|
||||
update_planes_and_stream_adapter(dm->dc,
|
||||
acrtc_state->update_type,
|
||||
planes_count,
|
||||
|
|
|
@ -980,6 +980,11 @@ static bool detect_link_and_local_sink(struct dc_link *link,
|
|||
(link->dpcd_caps.dongle_type !=
|
||||
DISPLAY_DONGLE_DP_HDMI_CONVERTER))
|
||||
converter_disable_audio = true;
|
||||
|
||||
/* limited link rate to HBR3 for DPIA until we implement USB4 V2 */
|
||||
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
|
||||
link->reported_link_cap.link_rate > LINK_RATE_HIGH3)
|
||||
link->reported_link_cap.link_rate = LINK_RATE_HIGH3;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
@ -1696,10 +1696,39 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
|
|||
}
|
||||
}
|
||||
|
||||
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
|
||||
workload_type = smu_cmn_to_asic_specific_index(smu,
|
||||
if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE &&
|
||||
(((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xC8)) ||
|
||||
((smu->adev->pdev->device == 0x744C) && (smu->adev->pdev->revision == 0xCC)))) {
|
||||
ret = smu_cmn_update_table(smu,
|
||||
SMU_TABLE_ACTIVITY_MONITOR_COEFF,
|
||||
WORKLOAD_PPLIB_COMPUTE_BIT,
|
||||
(void *)(&activity_monitor_external),
|
||||
false);
|
||||
if (ret) {
|
||||
dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = smu_cmn_update_table(smu,
|
||||
SMU_TABLE_ACTIVITY_MONITOR_COEFF,
|
||||
WORKLOAD_PPLIB_CUSTOM_BIT,
|
||||
(void *)(&activity_monitor_external),
|
||||
true);
|
||||
if (ret) {
|
||||
dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
workload_type = smu_cmn_to_asic_specific_index(smu,
|
||||
CMN2ASIC_MAPPING_WORKLOAD,
|
||||
PP_SMC_POWER_PROFILE_CUSTOM);
|
||||
} else {
|
||||
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
|
||||
workload_type = smu_cmn_to_asic_specific_index(smu,
|
||||
CMN2ASIC_MAPPING_WORKLOAD,
|
||||
smu->power_profile_mode);
|
||||
}
|
||||
|
||||
if (workload_type < 0)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
@ -307,6 +307,7 @@ static void radeon_fbdev_client_unregister(struct drm_client_dev *client)
|
|||
|
||||
if (fb_helper->info) {
|
||||
vga_switcheroo_client_fb_set(rdev->pdev, NULL);
|
||||
drm_helper_force_disable_all(dev);
|
||||
drm_fb_helper_unregister_info(fb_helper);
|
||||
} else {
|
||||
drm_client_release(&fb_helper->client);
|
||||
|
|
Loading…
Reference in New Issue