clk: samsung: Migrate exynos5420 to use common samsung_clk_register_pll()
This patch migrates exynos5420 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Yadwinder Singh Brar
Mike Turquette
parent
160641e718
commit
c898c6b7cb
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@ -17,13 +17,30 @@
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#include <linux/of_address.h>
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#include "clk.h"
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#include "clk-pll.h"
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#define APLL_LOCK 0x0
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#define APLL_CON0 0x100
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#define SRC_CPU 0x200
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#define DIV_CPU0 0x500
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#define DIV_CPU1 0x504
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#define GATE_BUS_CPU 0x700
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#define GATE_SCLK_CPU 0x800
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#define CPLL_LOCK 0x10020
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#define DPLL_LOCK 0x10030
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#define EPLL_LOCK 0x10040
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#define RPLL_LOCK 0x10050
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#define IPLL_LOCK 0x10060
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#define SPLL_LOCK 0x10070
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#define VPLL_LOCK 0x10070
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#define MPLL_LOCK 0x10090
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#define CPLL_CON0 0x10120
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#define DPLL_CON0 0x10128
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#define EPLL_CON0 0x10130
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#define RPLL_CON0 0x10140
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#define IPLL_CON0 0x10150
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#define SPLL_CON0 0x10160
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#define VPLL_CON0 0x10170
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#define MPLL_CON0 0x10180
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#define SRC_TOP0 0x10200
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#define SRC_TOP1 0x10204
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#define SRC_TOP2 0x10208
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@ -75,15 +92,27 @@
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#define GATE_TOP_SCLK_MAU 0x1083c
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#define GATE_TOP_SCLK_FSYS 0x10840
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#define GATE_TOP_SCLK_PERIC 0x10850
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#define BPLL_LOCK 0x20010
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#define BPLL_CON0 0x20110
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#define SRC_CDREX 0x20200
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#define KPLL_LOCK 0x28000
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#define KPLL_CON0 0x28100
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#define SRC_KFC 0x28200
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#define DIV_KFC0 0x28500
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/* list of PLLs */
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enum exynos5420_plls {
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apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
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bpll, kpll,
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nr_plls /* number of PLLs */
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};
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enum exynos5420_clks {
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none,
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/* core clocks */
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fin_pll,
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fin_pll, fout_apll, fout_cpll, fout_dpll, fout_epll, fout_rpll,
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fout_ipll, fout_spll, fout_vpll, fout_mpll, fout_bpll, fout_kpll,
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/* gate for special clocks (sclk) */
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sclk_uart0 = 128, sclk_uart1, sclk_uart2, sclk_uart3, sclk_mmc0,
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@ -698,6 +727,31 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
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GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
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};
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struct __initdata samsung_pll_clock exynos5420_plls[nr_plls] = {
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[apll] = PLL(pll_2550, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
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APLL_CON0),
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[cpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
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MPLL_CON0),
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[dpll] = PLL(pll_2550, fout_dpll, "fout_dpll", "fin_pll", DPLL_LOCK,
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DPLL_CON0),
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[epll] = PLL(pll_2650, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
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EPLL_CON0),
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[rpll] = PLL(pll_2650, fout_rpll, "fout_rpll", "fin_pll", RPLL_LOCK,
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RPLL_CON0),
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[ipll] = PLL(pll_2550, fout_ipll, "fout_ipll", "fin_pll", IPLL_LOCK,
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IPLL_CON0),
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[spll] = PLL(pll_2550, fout_spll, "fout_spll", "fin_pll", SPLL_LOCK,
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SPLL_CON0),
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[vpll] = PLL(pll_2550, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK,
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VPLL_CON0),
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[mpll] = PLL(pll_2550, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
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MPLL_CON0),
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[bpll] = PLL(pll_2550, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
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BPLL_CON0),
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[kpll] = PLL(pll_2550, fout_kpll, "fout_kpll", "fin_pll", KPLL_LOCK,
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KPLL_CON0),
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};
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static __initdata struct of_device_id ext_clk_match[] = {
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{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
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{ },
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@ -707,8 +761,6 @@ static __initdata struct of_device_id ext_clk_match[] = {
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static void __init exynos5420_clk_init(struct device_node *np)
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{
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void __iomem *reg_base;
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struct clk *apll, *bpll, *cpll, *dpll, *epll, *ipll, *kpll, *mpll;
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struct clk *rpll, *spll, *vpll;
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if (np) {
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reg_base = of_iomap(np, 0);
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@ -724,30 +776,8 @@ static void __init exynos5420_clk_init(struct device_node *np)
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samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks,
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ARRAY_SIZE(exynos5420_fixed_rate_ext_clks),
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ext_clk_match);
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apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
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reg_base + 0x100);
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bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
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reg_base + 0x20110);
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cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
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reg_base + 0x10120);
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dpll = samsung_clk_register_pll35xx("fout_dpll", "fin_pll",
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reg_base + 0x10128);
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epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
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reg_base + 0x10130);
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ipll = samsung_clk_register_pll35xx("fout_ipll", "fin_pll",
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reg_base + 0x10150);
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kpll = samsung_clk_register_pll35xx("fout_kpll", "fin_pll",
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reg_base + 0x28100);
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mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
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reg_base + 0x10180);
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rpll = samsung_clk_register_pll36xx("fout_rpll", "fin_pll",
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reg_base + 0x10140);
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spll = samsung_clk_register_pll35xx("fout_spll", "fin_pll",
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reg_base + 0x10160);
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vpll = samsung_clk_register_pll35xx("fout_vpll", "fin_pll",
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reg_base + 0x10170);
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samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls),
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reg_base);
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samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks,
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ARRAY_SIZE(exynos5420_fixed_rate_clks));
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samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks,
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