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powerpc/pseries: Define PCI bus speed for Gen4 and Gen5 

Update bus speed definition for PCI Gen4 and 5.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201130152949.26467-1-fbarrat@linux.ibm.com
This commit is contained in:
Frederic Barrat 2020-11-30 16:29:49 +01:00 committed by Michael Ellerman
parent 1baa1f70ef
commit c8754c517e
1 changed files with 21 additions and 30 deletions
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51
arch/powerpc/platforms/pseries/pci.c
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@ -290,6 +290,25 @@ static void fixup_winbond_82c105(struct pci_dev* dev)
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
fixup_winbond_82c105);
static enum pci_bus_speed prop_to_pci_speed(u32 prop)
{
switch (prop) {
case 0x01:
return PCIE_SPEED_2_5GT;
case 0x02:
return PCIE_SPEED_5_0GT;
case 0x04:
return PCIE_SPEED_8_0GT;
case 0x08:
return PCIE_SPEED_16_0GT;
case 0x10:
return PCIE_SPEED_32_0GT;
default:
pr_debug("Unexpected PCI link speed property value\n");
return PCI_SPEED_UNKNOWN;
}
}
int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
{
struct device_node *dn, *pdn;
@ -322,35 +341,7 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
return 0;
}
switch (pcie_link_speed_stats[0]) {
case 0x01:
bus->max_bus_speed = PCIE_SPEED_2_5GT;
break;
case 0x02:
bus->max_bus_speed = PCIE_SPEED_5_0GT;
break;
case 0x04:
bus->max_bus_speed = PCIE_SPEED_8_0GT;
break;
default:
bus->max_bus_speed = PCI_SPEED_UNKNOWN;
break;
}
switch (pcie_link_speed_stats[1]) {
case 0x01:
bus->cur_bus_speed = PCIE_SPEED_2_5GT;
break;
case 0x02:
bus->cur_bus_speed = PCIE_SPEED_5_0GT;
break;
case 0x04:
bus->cur_bus_speed = PCIE_SPEED_8_0GT;
break;
default:
bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
break;
}
bus->max_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[0]);
bus->cur_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[1]);
return 0;
}