AT91 & LAN966 DT #1 for 5.18:
- lan966x basic DT and associated evaluation board pcb8291 (2-ports) - documentation for an upcoming Kontron switch board featuring a LAN9668 - one fix for an old bug we have with PMECC on sama5d2 in some corner cases - sama7g5 and its EK: crypto, CAN and DVFS operating points -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCYhi3WQAKCRAfOrpwrNPN DOTGAP9y9/HV8EXrGhm8ZvH0ScfIkf3cPFyoFKtcN4EFNKb12QD/aSjSW17XEwTt L+RYm2x2lha8eVUteyRpZXZqmK8buwg= =3qii -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8xQACgkQmmx57+YA GNmEyg//ej6i6g/4dVcG1TQ+Fm4zSm19HM338FduYw2esH0P6pgUKG+V6sOBaFWF m2HaHPTsbaY90mshpym6rmC22UwEsdw64x5Z4en20NRrdLBjraVzLltz8UhLAEH2 +/pjw0CU/CxRE1z+OItfdElg3+HyJuPyF7rjXXCsM3DIMZzOR8CEXO9tt+K2EJKQ LgO5cz4a0lS6a0FUdXivq1jzRmQW2sUzvA+7XQ/KKczxLiNzgVWD92ysua9pzoBp a1eOrpr9BD2PpYawLlBQB995NjRCvgCf4P8QJDbjrOpfmbM13AqFi4Yk7LbKIY+d kvqp7Ru9Zbbvg7WW276jQOMbD53/AkmJEaomKsEJeazpvOOiDnMKsY5y0PZ8Ma/f +HSjAoXUSGw1x3+o/Ai8LlnOU6SXYo95OgmEz/KOpw08lBOkyWT2jSWEF+7bLHDg zw0vUQESSNsGMlfH1xWit9MLqlyr/WanAhQW3CKvsFfd8IEEo7dcA/djjWsTVgiS R5F9qJwq5/MLpxSESRJrUiVg5zBALEToHAdL+TsRD6aU0yBhsawaPQG2vWtCOdTw GIzY4GdYMo3izMDNaxcf+/ku/AjuCzTJGO73BKGrrY/e9Rk3vTBlNTp7FGBRxpb5 tu+X2uyXu8cMqzHcO/UYX7WN9OjVSIwFhS2Hf/3joK8ETxGpyy4= =+JfK -----END PGP SIGNATURE----- Merge tag 'at91-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 & LAN966 DT #1 for 5.18: - lan966x basic DT and associated evaluation board pcb8291 (2-ports) - documentation for an upcoming Kontron switch board featuring a LAN9668 - one fix for an old bug we have with PMECC on sama5d2 in some corner cases - sama7g5 and its EK: crypto, CAN and DVFS operating points * tag 'at91-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: at91: sama7g5: add opps ARM: dts: at91: sama7g5ek: set regulator voltages for standby state ARM: dts: at91: fix low limit for CPU regulator ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ek ARM: dts: at91: sama7g5: Add can controllers of sama7g5 ARM: dts: at91: sama7g5: Add crypto nodes ARM: dts: at91: Use the generic "crypto" node name for the crypto IPs ARM: dts: at91: remove status = "okay" from soc specific dtsi ARM: dts: at91: sama5d2: Fix PMERRLOC resource size dt-bindings: arm: at91: add Kontron's new KSwitches ARM: dts: add DT for lan966 SoC and 2-port board pcb8291 Link: https://lore.kernel.org/r/20220225110735.18080-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c845b55859
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@ -174,6 +174,15 @@ properties:
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- const: microchip,lan9668
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- const: microchip,lan966
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- description: Kontron KSwitch D10 MMT series
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items:
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- enum:
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- kontron,kswitch-d10-mmt-8g
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- kontron,kswitch-d10-mmt-6g-2gs
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- const: kontron,s1921
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- const: microchip,lan9668
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- const: microchip,lan966
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- items:
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- enum:
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- atmel,sams70j19
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@ -737,6 +737,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
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dtb-$(CONFIG_SOC_IMX7ULP) += \
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imx7ulp-com.dtb \
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imx7ulp-evk.dtb
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dtb-$(CONFIG_SOC_LAN966) += \
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lan966x-pcb8291.dtb
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dtb-$(CONFIG_SOC_LS1021A) += \
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ls1021a-moxa-uc-8410a.dtb \
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ls1021a-qds.dtb \
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@ -131,6 +131,18 @@
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status = "okay";
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};
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&can0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0_default>;
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1_default>;
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status = "okay";
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};
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&cpu0 {
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cpu-supply = <&vddcpu>;
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};
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@ -239,6 +251,7 @@
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regulator-state-standby {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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regulator-mode = <4>;
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};
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@ -279,6 +292,7 @@
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regulator-state-standby {
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regulator-on-in-suspend;
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regulator-suspend-voltage = <1150000>;
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regulator-mode = <4>;
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};
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@ -290,7 +304,7 @@
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vddcpu: VDD_OTHER {
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regulator-name = "VDD_OTHER";
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regulator-min-microvolt = <1125000>;
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regulator-min-microvolt = <1050000>;
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regulator-max-microvolt = <1850000>;
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regulator-initial-mode = <2>;
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regulator-allowed-modes = <2>, <4>;
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@ -299,6 +313,7 @@
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regulator-state-standby {
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regulator-on-in-suspend;
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regulator-suspend-voltage = <1050000>;
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regulator-mode = <4>;
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};
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@ -315,6 +330,7 @@
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regulator-always-on;
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regulator-state-standby {
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regulator-suspend-voltage = <1800000>;
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regulator-on-in-suspend;
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};
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@ -329,6 +345,7 @@
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regulator-max-microvolt = <3700000>;
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regulator-state-standby {
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regulator-suspend-voltage = <1800000>;
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regulator-on-in-suspend;
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};
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@ -454,6 +471,19 @@
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};
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&pioA {
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pinctrl_can0_default: can0_default {
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pinmux = <PIN_PD12__CANTX0>,
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<PIN_PD13__CANRX0 >;
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bias-disable;
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};
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pinctrl_can1_default: can1_default {
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pinmux = <PIN_PD14__CANTX1>,
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<PIN_PD15__CANRX1 >;
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bias-disable;
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};
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pinctrl_flx0_default: flx0_default {
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pinmux = <PIN_PE3__FLEXCOM0_IO0>,
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<PIN_PE4__FLEXCOM0_IO1>,
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@ -0,0 +1,64 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* lan966x_pcb8291.dts - Device Tree file for PCB8291
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*/
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/dts-v1/;
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#include "lan966x.dtsi"
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/ {
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model = "Microchip EVB - LAN9662";
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compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &usart3;
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};
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};
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&gpio {
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fc_shrd7_pins: fc_shrd7-pins {
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pins = "GPIO_49";
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function = "fc_shrd7";
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};
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fc_shrd8_pins: fc_shrd8-pins {
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pins = "GPIO_54";
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function = "fc_shrd8";
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};
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fc3_b_pins: fcb3-spi-pins {
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/* SCK, RXD, TXD */
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pins = "GPIO_51", "GPIO_52", "GPIO_53";
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function = "fc3_b";
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};
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can0_b_pins: can0_b_pins {
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/* RX, TX */
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pins = "GPIO_35", "GPIO_36";
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function = "can0_b";
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};
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};
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&can0 {
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pinctrl-0 = <&can0_b_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&flx3 {
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atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
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status = "okay";
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usart3: serial@200 {
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pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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};
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&watchdog {
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status = "okay";
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};
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@ -0,0 +1,237 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
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*
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* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
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*
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* Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mfd/atmel-flexcom.h>
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/microchip,lan966x.h>
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/ {
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model = "Microchip LAN966 family SoC";
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compatible = "microchip,lan966";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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clock-frequency = <600000000>;
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reg = <0x0>;
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};
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};
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clocks {
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sys_clk: sys_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <162500000>;
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};
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cpu_clk: cpu_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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};
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ddr_clk: ddr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <300000000>;
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};
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nic_clk: nic_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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clks: clock-controller@e00c00a8 {
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compatible = "microchip,lan966x-gck";
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#clock-cells = <1>;
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clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
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clock-names = "cpu", "ddr", "sys";
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reg = <0xe00c00a8 0x38>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <37500000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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flx0: flexcom@e0040000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0040000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0040000 0x800>;
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status = "disabled";
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};
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flx1: flexcom@e0044000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0044000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0044000 0x800>;
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status = "disabled";
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};
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trng: rng@e0048000 {
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compatible = "atmel,at91sam9g45-trng";
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reg = <0xe0048000 0x100>;
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clocks = <&nic_clk>;
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};
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aes: crypto@e004c000 {
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compatible = "atmel,at91sam9g46-aes";
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reg = <0xe004c000 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
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<&dma0 AT91_XDMAC_DT_PERID(12)>;
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dma-names = "rx", "tx";
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clocks = <&nic_clk>;
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clock-names = "aes_clk";
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};
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flx2: flexcom@e0060000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0060000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM2>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0060000 0x800>;
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status = "disabled";
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};
|
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flx3: flexcom@e0064000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0064000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM3>;
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#address-cells = <1>;
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#size-cells = <1>;
|
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ranges = <0x0 0xe0064000 0x800>;
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status = "disabled";
|
||||
|
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usart3: serial@200 {
|
||||
compatible = "atmel,at91sam9260-usart";
|
||||
reg = <0x200 0x200>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&nic_clk>;
|
||||
clock-names = "usart";
|
||||
atmel,fifo-size = <32>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dma0: dma-controller@e0068000 {
|
||||
compatible = "microchip,sama7g5-dma";
|
||||
reg = <0xe0068000 0x1000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
clocks = <&nic_clk>;
|
||||
clock-names = "dma_clk";
|
||||
};
|
||||
|
||||
sha: crypto@e006c000 {
|
||||
compatible = "atmel,at91sam9g46-sha";
|
||||
reg = <0xe006c000 0xec>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
|
||||
dma-names = "tx";
|
||||
clocks = <&nic_clk>;
|
||||
clock-names = "sha_clk";
|
||||
};
|
||||
|
||||
flx4: flexcom@e0070000 {
|
||||
compatible = "atmel,sama5d2-flexcom";
|
||||
reg = <0xe0070000 0x100>;
|
||||
clocks = <&clks GCK_ID_FLEXCOM4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xe0070000 0x800>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer0: timer@e008c000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0xe008c000 0x400>;
|
||||
clocks = <&nic_clk>;
|
||||
clock-names = "timer";
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
watchdog: watchdog@e0090000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0xe0090000 0x1000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&nic_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can0: can@e081c000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&clks GCK_ID_MCAN0>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio: pinctrl@e2004064 {
|
||||
compatible = "microchip,lan966x-pinctrl";
|
||||
reg = <0xe2004064 0xb4>,
|
||||
<0xe2010024 0x138>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&gpio 0 0 78>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@e8c11000 {
|
||||
compatible = "arm,gic-400", "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
reg = <0xe8c11000 0x1000>,
|
||||
<0xe8c12000 0x2000>,
|
||||
<0xe8c14000 0x2000>,
|
||||
<0xe8c16000 0x2000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -270,7 +270,7 @@
|
|||
clock-names = "pclk", "gclk";
|
||||
};
|
||||
|
||||
sha: sha@f002c000 {
|
||||
sha: crypto@f002c000 {
|
||||
compatible = "atmel,at91sam9g46-sha";
|
||||
reg = <0xf002c000 0x100>;
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -280,7 +280,6 @@
|
|||
dma-names = "tx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
|
||||
clock-names = "sha_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
trng: trng@f0030000 {
|
||||
|
|
@ -288,10 +287,9 @@
|
|||
reg = <0xf0030000 0x100>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
aes: aes@f0034000 {
|
||||
aes: crypto@f0034000 {
|
||||
compatible = "atmel,at91sam9g46-aes";
|
||||
reg = <0xf0034000 0x100>;
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -304,10 +302,9 @@
|
|||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
|
||||
clock-names = "aes_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tdes: tdes@f0038000 {
|
||||
tdes: crypto@f0038000 {
|
||||
compatible = "atmel,at91sam9g46-tdes";
|
||||
reg = <0xf0038000 0x100>;
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -320,7 +317,6 @@
|
|||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
|
||||
clock-names = "tdes_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
classd: classd@f003c000 {
|
||||
|
|
|
|||
|
|
@ -306,7 +306,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sha@f0028000 {
|
||||
sha: crypto@f0028000 {
|
||||
compatible = "atmel,at91sam9g46-sha";
|
||||
reg = <0xf0028000 0x100>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -316,10 +316,9 @@
|
|||
dma-names = "tx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
|
||||
clock-names = "sha_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
aes@f002c000 {
|
||||
aes: crypto@f002c000 {
|
||||
compatible = "atmel,at91sam9g46-aes";
|
||||
reg = <0xf002c000 0x100>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -332,7 +331,6 @@
|
|||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
|
||||
clock-names = "aes_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@f8000000 {
|
||||
|
|
@ -415,7 +413,7 @@
|
|||
pmecc: ecc-engine@f8014070 {
|
||||
compatible = "atmel,sama5d2-pmecc";
|
||||
reg = <0xf8014070 0x490>,
|
||||
<0xf8014500 0x100>;
|
||||
<0xf8014500 0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1084,7 +1082,7 @@
|
|||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
tdes@fc044000 {
|
||||
tdes: crypto@fc044000 {
|
||||
compatible = "atmel,at91sam9g46-tdes";
|
||||
reg = <0xfc044000 0x100>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -1097,7 +1095,6 @@
|
|||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
|
||||
clock-names = "tdes_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
classd: classd@fc048000 {
|
||||
|
|
|
|||
|
|
@ -381,7 +381,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sha@f8034000 {
|
||||
sha: crypto@f8034000 {
|
||||
compatible = "atmel,at91sam9g46-sha";
|
||||
reg = <0xf8034000 0x100>;
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -391,7 +391,7 @@
|
|||
clock-names = "sha_clk";
|
||||
};
|
||||
|
||||
aes@f8038000 {
|
||||
aes: crypto@f8038000 {
|
||||
compatible = "atmel,at91sam9g46-aes";
|
||||
reg = <0xf8038000 0x100>;
|
||||
interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -402,7 +402,7 @@
|
|||
clock-names = "aes_clk";
|
||||
};
|
||||
|
||||
tdes@f803c000 {
|
||||
tdes: crypto@f803c000 {
|
||||
compatible = "atmel,at91sam9g46-tdes";
|
||||
reg = <0xf803c000 0x100>;
|
||||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
|
|||
|
|
@ -673,7 +673,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
aes@fc044000 {
|
||||
aes: crypto@fc044000 {
|
||||
compatible = "atmel,at91sam9g46-aes";
|
||||
reg = <0xfc044000 0x100>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -684,10 +684,9 @@
|
|||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
|
||||
clock-names = "aes_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tdes@fc04c000 {
|
||||
tdes: crpyto@fc04c000 {
|
||||
compatible = "atmel,at91sam9g46-tdes";
|
||||
reg = <0xfc04c000 0x100>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -698,10 +697,9 @@
|
|||
dma-names = "tx", "rx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
|
||||
clock-names = "tdes_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sha@fc050000 {
|
||||
sha: crypto@fc050000 {
|
||||
compatible = "atmel,at91sam9g46-sha";
|
||||
reg = <0xfc050000 0x100>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
|
@ -710,7 +708,6 @@
|
|||
dma-names = "tx";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
|
||||
clock-names = "sha_clk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hsmc: smc@fc05c000 {
|
||||
|
|
|
|||
|
|
@ -30,6 +30,44 @@
|
|||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
|
||||
clock-names = "cpu";
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-90000000 {
|
||||
opp-hz = /bits/ 64 <90000000>;
|
||||
opp-microvolt = <1050000 1050000 1225000>;
|
||||
clock-latency-ns = <320000>;
|
||||
};
|
||||
|
||||
opp-250000000 {
|
||||
opp-hz = /bits/ 64 <250000000>;
|
||||
opp-microvolt = <1050000 1050000 1225000>;
|
||||
clock-latency-ns = <320000>;
|
||||
};
|
||||
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-microvolt = <1050000 1050000 1225000>;
|
||||
clock-latency-ns = <320000>;
|
||||
opp-suspend;
|
||||
};
|
||||
|
||||
opp-800000000 {
|
||||
opp-hz = /bits/ 64 <800000000>;
|
||||
opp-microvolt = <1150000 1125000 1225000>;
|
||||
clock-latency-ns = <320000>;
|
||||
};
|
||||
|
||||
opp-1000000002 {
|
||||
opp-hz = /bits/ 64 <1000000002>;
|
||||
opp-microvolt = <1250000 1225000 1300000>;
|
||||
clock-latency-ns = <320000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -83,7 +121,6 @@
|
|||
#size-cells = <1>;
|
||||
ranges = <0 0xe0000000 0x4000>;
|
||||
no-memory-wc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
secumod: secumod@e0004000 {
|
||||
|
|
@ -211,6 +248,102 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
can0: can@e0828000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xe0828000 0x100>, <0x100000 0x7800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e082c000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can2: can@e0830000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xe0830000 0x100>, <0x100000 0x10000>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can3: can@e0834000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xe0834000 0x100>, <0x110000 0x4400>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can4: can@e0838000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xe0838000 0x100>, <0x110000 0x8800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can5: can@e083c000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
|
||||
clock-names = "hclk", "cclk";
|
||||
assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
|
||||
assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc: adc@e1000000 {
|
||||
compatible = "microchip,sama7g5-adc";
|
||||
reg = <0xe1000000 0x200>;
|
||||
|
|
@ -338,6 +471,27 @@
|
|||
clock-names = "pclk", "gclk";
|
||||
};
|
||||
|
||||
aes: crypto@e1810000 {
|
||||
compatible = "atmel,at91sam9g46-aes";
|
||||
reg = <0xe1810000 0x100>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
|
||||
clock-names = "aes_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
|
||||
<&dma0 AT91_XDMAC_DT_PERID(2)>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
sha: crypto@e1814000 {
|
||||
compatible = "atmel,at91sam9g46-sha";
|
||||
reg = <0xe1814000 0x100>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
|
||||
clock-names = "sha_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
|
||||
flx0: flexcom@e1818000 {
|
||||
compatible = "atmel,sama5d2-flexcom";
|
||||
reg = <0xe1818000 0x200>;
|
||||
|
|
@ -420,6 +574,17 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
tdes: crypto@e2014000 {
|
||||
compatible = "atmel,at91sam9g46-tdes";
|
||||
reg = <0xe2014000 0x100>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
|
||||
clock-names = "tdes_clk";
|
||||
dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
|
||||
<&dma0 AT91_XDMAC_DT_PERID(53)>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
flx4: flexcom@e2018000 {
|
||||
compatible = "atmel,sama5d2-flexcom";
|
||||
reg = <0xe2018000 0x200>;
|
||||
|
|
@ -618,13 +783,11 @@
|
|||
uddrc: uddrc@e3800000 {
|
||||
compatible = "microchip,sama7g5-uddrc";
|
||||
reg = <0xe3800000 0x4000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ddr3phy: ddr3phy@e3804000 {
|
||||
compatible = "microchip,sama7g5-ddr3phy";
|
||||
reg = <0xe3804000 0x1000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@e8c11000 {
|
||||
|
|
|
|||
Loading…
Reference in New Issue