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clk: qcom: Base rcg parent rate off plan frequency 

_freq_tbl_determine_rate uses the pre_div found in the clock plan
multiplied by the requested rate from the caller to determine the
best parent rate to set. If the requested rate is not exactly equal
to the rate that was found in the clock plan, then using the requested
rate in parent rate calculations is incorrect. For instance, if 150MHz
was requested, but 200MHz was the match found, and that plan had a
pre_div of 3, then the parent should be set to 600MHz, not 450MHz.

Signed-off-by: Evan Green <evgreen@chromium.org>
Fixes: bcd61c0f53 ("clk: qcom: Add support for root clock generators (RCGs)")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Evan Green 2018-04-13 13:33:36 -07:00 committed by Stephen Boyd
parent 60cc43fc88
commit c7d2a0eb6c
1 changed files with 1 additions and 0 deletions
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1
drivers/clk/qcom/clk-rcg2.c
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@ -211,6 +211,7 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
clk_flags = clk_hw_get_flags(hw); clk_flags = clk_hw_get_flags(hw);
p = clk_hw_get_parent_by_index(hw, index); p = clk_hw_get_parent_by_index(hw, index);
if (clk_flags & CLK_SET_RATE_PARENT) { if (clk_flags & CLK_SET_RATE_PARENT) {
rate = f->freq;
if (f->pre_div) { if (f->pre_div) {
rate /= 2; rate /= 2;
rate *= f->pre_div + 1; rate *= f->pre_div + 1;