Devicetree fixes for 5.3:
Fix several warnings/errors in validation of binding schemas. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAl0zzmkQHHJvYmhAa2Vy bmVsLm9yZwAKCRD6+121jbxhw0YYD/9Uq8Oj9WG9NP8QeJt1qZIVIu4GMRqCiijM ApXu9RAsQvaakwRiqaOufFSACIP/yjxHadbncObMWq7uGLT2TVxZwhR8XeOoi+Ft UO/2KosTbTpMeAjFB1Dz/f0IbUa4Ro5ZiP5kohGNi5X/IdsCAC0ypFk3cCIx4Siz /gr+cN+ef9p6cOy+vGzEGRMSDULbun/9cZmctDpMf9ZFUMu8xA/nn6qTEck3mQ2j OX465qPGrstZKlO3C2NVSyUip8/NLhTrUeDCCNTFw6fOIxRCjQfIj0MNMnm+pjO3 /xPDQV0Swv+LjT+HSJA8TyEXKQP28N+v9K9bP4e59PPAf2raGX1khwvMM5bJuy// 2K8mDmAJrP5wy/9aFq8bPdzWQZzfPefDW1PCBNtZybo6OlppDu+4uX7FonjRI/nj 7AzS3qch4v4i1sJmADgysn9yOUgzUvJf/SLD1f5XHsiEa0RXr51QWVxvJaRs24wS U/vzyZq6vqtTBSOzXpjIK0Yj+D7f05qT0MsPK5lbynCdByLli3xhbte8AwGg57RW 4CtPTZLdPVvIlCZ3jNOZXq9OizRSBokaj155YvSKQ9nzcnbHfEF4JctJQ+K3tdwS 6s4FVrgNxtXN9KidfBCnWDj+1eS1ZxeCmKo1Ypxhj9/t80NXt7b7dwEJ8H91/YuU GfLancHPHQ== =IkH4 -----END PGP SIGNATURE----- Merge tag 'devicetree-fixes-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull Devicetree fixes from Rob Herring: "Fix several warnings/errors in validation of binding schemas" * tag 'devicetree-fixes-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: pinctrl: stm32: Fix missing 'clocks' property in examples dt-bindings: iio: ad7124: Fix dtc warnings in example dt-bindings: iio: avia-hx711: Fix avdd-supply typo in example dt-bindings: pinctrl: aspeed: Fix AST2500 example errors dt-bindings: pinctrl: aspeed: Fix 'compatible' schema errors dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes dt-bindings: Ensure child nodes are of type 'object'
This commit is contained in:
commit
c7bf0a0f37
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@ -42,6 +42,7 @@ properties:
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patternProperties:
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"^.*@[0-9a-fA-F]+$":
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type: object
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properties:
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reg:
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maxItems: 1
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@ -114,42 +114,47 @@ patternProperties:
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examples:
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- |
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adc@0 {
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compatible = "adi,ad7124-4";
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reg = <0>;
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spi-max-frequency = <5000000>;
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interrupts = <25 2>;
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interrupt-parent = <&gpio>;
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refin1-supply = <&adc_vref>;
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clocks = <&ad7124_mclk>;
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clock-names = "mclk";
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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adc@0 {
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compatible = "adi,ad7124-4";
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reg = <0>;
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diff-channels = <0 1>;
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adi,reference-select = <0>;
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adi,buffered-positive;
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};
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spi-max-frequency = <5000000>;
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interrupts = <25 2>;
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interrupt-parent = <&gpio>;
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refin1-supply = <&adc_vref>;
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clocks = <&ad7124_mclk>;
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clock-names = "mclk";
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channel@1 {
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reg = <1>;
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bipolar;
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diff-channels = <2 3>;
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adi,reference-select = <0>;
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adi,buffered-positive;
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adi,buffered-negative;
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};
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#address-cells = <1>;
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#size-cells = <0>;
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channel@2 {
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reg = <2>;
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diff-channels = <4 5>;
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};
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channel@0 {
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reg = <0>;
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diff-channels = <0 1>;
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adi,reference-select = <0>;
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adi,buffered-positive;
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};
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channel@3 {
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reg = <3>;
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diff-channels = <6 7>;
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channel@1 {
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reg = <1>;
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bipolar;
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diff-channels = <2 3>;
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adi,reference-select = <0>;
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adi,buffered-positive;
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adi,buffered-negative;
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};
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channel@2 {
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reg = <2>;
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diff-channels = <4 5>;
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};
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channel@3 {
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reg = <3>;
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diff-channels = <6 7>;
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};
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};
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};
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@ -61,6 +61,6 @@ examples:
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compatible = "avia,hx711";
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sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
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dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
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avdd-suppy = <&avdd>;
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avdd-supply = <&avdd>;
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clock-frequency = <100000>;
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};
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@ -55,6 +55,7 @@ patternProperties:
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"^pinctrl-[0-9]+$": true
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"^nand@[a-f0-9]+$":
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type: object
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properties:
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reg:
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minimum: 0
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@ -40,6 +40,7 @@ properties:
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patternProperties:
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"^nand@[a-f0-9]$":
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type: object
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properties:
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reg:
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description:
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@ -22,7 +22,9 @@ description: |+
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properties:
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compatible:
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enum: [ aspeed,ast2400-pinctrl, aspeed,g4-pinctrl ]
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enum:
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- aspeed,ast2400-pinctrl
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- aspeed,g4-pinctrl
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patternProperties:
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'^.*$':
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@ -22,7 +22,9 @@ description: |+
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properties:
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compatible:
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enum: [ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl ]
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enum:
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- aspeed,ast2500-pinctrl
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- aspeed,g5-pinctrl
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aspeed,external-nodes:
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minItems: 2
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maxItems: 2
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@ -74,9 +76,6 @@ required:
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examples:
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- |
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compatible = "simple-bus";
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ranges;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -89,7 +88,7 @@ examples:
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pinctrl: pinctrl {
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compatible = "aspeed,g5-pinctrl";
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aspeed,external-nodes = <&gfx &lhc>;
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aspeed,external-nodes = <&gfx>, <&lhc>;
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pinctrl_i2c3_default: i2c3_default {
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function = "I2C3";
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@ -55,6 +55,7 @@ properties:
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patternProperties:
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'^gpio@[0-9a-f]*$':
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type: object
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properties:
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gpio-controller: true
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'#gpio-cells':
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@ -113,8 +114,10 @@ patternProperties:
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- st,bank-name
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'-[0-9]*$':
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type: object
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patternProperties:
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'^pins':
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type: object
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description: |
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A pinctrl node should contain at least one subnode representing the
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pinctrl group available on the machine. Each subnode will list the
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@ -194,6 +197,7 @@ required:
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examples:
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- |
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/mfd/stm32f4-rcc.h>
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//Example 1
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pinctrl@40020000 {
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#address-cells = <1>;
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@ -207,6 +211,7 @@ examples:
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#gpio-cells = <2>;
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reg = <0x0 0x400>;
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resets = <&reset_ahb1 0>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
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st,bank-name = "GPIOA";
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};
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};
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@ -224,6 +229,7 @@ examples:
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#gpio-cells = <2>;
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reg = <0x1000 0x400>;
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resets = <&reset_ahb1 0>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
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st,bank-name = "GPIOB";
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gpio-ranges = <&pinctrl 0 0 16>;
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};
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@ -233,6 +239,7 @@ examples:
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#gpio-cells = <2>;
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reg = <0x2000 0x400>;
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resets = <&reset_ahb1 0>;
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clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
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st,bank-name = "GPIOC";
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ngpios = <5>;
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gpio-ranges = <&pinctrl 0 16 3>,
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@ -10,97 +10,76 @@ maintainers:
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Palmer Dabbelt <palmer@sifive.com>
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allOf:
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- $ref: /schemas/cpus.yaml#
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properties:
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$nodename:
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const: cpus
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description: Container of cpu nodes
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compatible:
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items:
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- enum:
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- sifive,rocket0
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- sifive,e5
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- sifive,e51
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- sifive,u54-mc
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- sifive,u54
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- sifive,u5
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- const: riscv
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description:
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Identifies that the hart uses the RISC-V instruction set
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and identifies the type of the hart.
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'#address-cells':
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const: 1
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description: |
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A single unsigned 32-bit integer uniquely identifies each RISC-V
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hart in a system. (See the "reg" node under the "cpu" node,
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below).
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mmu-type:
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/string"
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- enum:
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- riscv,sv32
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- riscv,sv39
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- riscv,sv48
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description:
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Identifies the MMU address translation mode used on this
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hart. These values originate from the RISC-V Privileged
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Specification document, available from
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https://riscv.org/specifications/
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'#size-cells':
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const: 0
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riscv,isa:
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/string"
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- enum:
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- rv64imac
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- rv64imafdc
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description:
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Identifies the specific RISC-V instruction set architecture
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supported by the hart. These are documented in the RISC-V
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User-Level ISA document, available from
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https://riscv.org/specifications/
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timebase-frequency:
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type: integer
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minimum: 1
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description:
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Specifies the clock frequency of the system timer in Hz.
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This value is common to all harts on a single system image.
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interrupt-controller:
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type: object
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description: Describes the CPU's local interrupt controller
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patternProperties:
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'^cpu@[0-9a-f]+$':
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properties:
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'#interrupt-cells':
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const: 1
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compatible:
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type: array
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items:
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- enum:
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- sifive,rocket0
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- sifive,e5
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- sifive,e51
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- sifive,u54-mc
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- sifive,u54
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- sifive,u5
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- const: riscv
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description:
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Identifies that the hart uses the RISC-V instruction set
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and identifies the type of the hart.
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const: riscv,cpu-intc
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mmu-type:
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/string"
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- enum:
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- riscv,sv32
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- riscv,sv39
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- riscv,sv48
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description:
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Identifies the MMU address translation mode used on this
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hart. These values originate from the RISC-V Privileged
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Specification document, available from
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https://riscv.org/specifications/
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riscv,isa:
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allOf:
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- $ref: "/schemas/types.yaml#/definitions/string"
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- enum:
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- rv64imac
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- rv64imafdc
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description:
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Identifies the specific RISC-V instruction set architecture
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supported by the hart. These are documented in the RISC-V
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User-Level ISA document, available from
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https://riscv.org/specifications/
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timebase-frequency:
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type: integer
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minimum: 1
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description:
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Specifies the clock frequency of the system timer in Hz.
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This value is common to all harts on a single system image.
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interrupt-controller:
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type: object
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description: Describes the CPU's local interrupt controller
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properties:
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'#interrupt-cells':
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const: 1
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compatible:
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const: riscv,cpu-intc
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interrupt-controller: true
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required:
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- '#interrupt-cells'
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- compatible
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- interrupt-controller
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interrupt-controller: true
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required:
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- riscv,isa
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- timebase-frequency
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- '#interrupt-cells'
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- compatible
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- interrupt-controller
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required:
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- riscv,isa
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- timebase-frequency
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- interrupt-controller
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examples:
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- |
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// Example 1: SiFive Freedom U540G Development Kit
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@ -50,6 +50,7 @@ properties:
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patternProperties:
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"^.*@[0-9a-f]+":
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type: object
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properties:
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reg:
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items:
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@ -55,6 +55,7 @@ properties:
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patternProperties:
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"^.*@[0-9a-f]+":
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type: object
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properties:
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reg:
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items:
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