arm64: dts: sdm845: Add gpu and gmu device nodes
Add the nodes to describe the Adreno GPU and GMU devices for sdm845. Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> [bjorn: Added required gx power-domain] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <agross@kernel.org>
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@ -2104,6 +2104,129 @@
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gpu@5000000 {
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compatible = "qcom,adreno-630.2", "qcom,adreno";
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#stream-id-cells = <16>;
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reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
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reg-names = "kgsl_3d0_reg_memory", "cx_mem";
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/*
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* Look ma, no clocks! The GPU clocks and power are
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* controlled entirely by the GMU
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*/
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interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&adreno_smmu 0>;
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operating-points-v2 = <&gpu_opp_table>;
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qcom,gmu = <&gmu>;
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gpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-710000000 {
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opp-hz = /bits/ 64 <710000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
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};
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opp-675000000 {
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opp-hz = /bits/ 64 <675000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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opp-596000000 {
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opp-hz = /bits/ 64 <596000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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opp-520000000 {
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opp-hz = /bits/ 64 <520000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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opp-414000000 {
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opp-hz = /bits/ 64 <414000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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opp-342000000 {
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opp-hz = /bits/ 64 <342000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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opp-257000000 {
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opp-hz = /bits/ 64 <257000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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};
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};
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adreno_smmu: iommu@5040000 {
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compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
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reg = <0 0x5040000 0 0x10000>;
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#iommu-cells = <1>;
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#global-interrupts = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
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clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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<&gcc GCC_GPU_CFG_AHB_CLK>;
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clock-names = "bus", "iface";
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power-domains = <&gpucc GPU_CX_GDSC>;
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};
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gmu: gmu@506a000 {
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compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
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reg = <0 0x506a000 0 0x30000>,
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<0 0xb280000 0 0x10000>,
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<0 0xb480000 0 0x10000>;
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reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
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interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hfi", "gmu";
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clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
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<&gpucc GPU_CC_CXO_CLK>,
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<&gcc GCC_DDRSS_GPU_AXI_CLK>,
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<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
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clock-names = "gmu", "cxo", "axi", "memnoc";
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power-domains = <&gpucc GPU_CX_GDSC>,
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<&gpucc GPU_GX_GDSC>;
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power-domain-names = "cx", "gx";
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iommus = <&adreno_smmu 5>;
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operating-points-v2 = <&gmu_opp_table>;
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gmu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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};
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};
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};
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dispcc: clock-controller@af00000 {
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dispcc: clock-controller@af00000 {
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compatible = "qcom,sdm845-dispcc";
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compatible = "qcom,sdm845-dispcc";
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reg = <0 0x0af00000 0 0x10000>;
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reg = <0 0x0af00000 0 0x10000>;
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