irqchip/apple-aic: Wire PMU interrupts
Add the necessary code to configure and P and E-core PMU interrupts with their respective affinities. When such an interrupt fires, map it onto the right pseudo-interrupt. Reviewed-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org>
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@ -155,7 +155,7 @@
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#define SYS_IMP_APL_UPMSR_EL1 sys_reg(3, 7, 15, 6, 4)
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#define UPMSR_IACT BIT(0)
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#define AIC_NR_FIQ 4
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#define AIC_NR_FIQ 6
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#define AIC_NR_SWIPI 32
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/*
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@ -415,16 +415,15 @@ static void __exception_irq_entry aic_handle_fiq(struct pt_regs *regs)
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aic_irqc->nr_hw + AIC_TMR_EL02_VIRT);
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}
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if ((read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & (PMCR0_IMODE | PMCR0_IACT)) ==
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(FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_FIQ) | PMCR0_IACT)) {
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/*
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* Not supported yet, let's figure out how to handle this when
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* we implement these proprietary performance counters. For now,
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* just mask it and move on.
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*/
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pr_err_ratelimited("PMC FIQ fired. Masking.\n");
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sysreg_clear_set_s(SYS_IMP_APL_PMCR0_EL1, PMCR0_IMODE | PMCR0_IACT,
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FIELD_PREP(PMCR0_IMODE, PMCR0_IMODE_OFF));
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if (read_sysreg_s(SYS_IMP_APL_PMCR0_EL1) & PMCR0_IACT) {
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int irq;
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if (cpumask_test_cpu(smp_processor_id(),
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&aic_irqc->fiq_aff[AIC_CPU_PMU_P]->aff))
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irq = AIC_CPU_PMU_P;
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else
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irq = AIC_CPU_PMU_E;
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generic_handle_domain_irq(aic_irqc->hw_domain,
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aic_irqc->nr_hw + irq);
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}
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if (FIELD_GET(UPMCR0_IMODE, read_sysreg_s(SYS_IMP_APL_UPMCR0_EL1)) == UPMCR0_IMODE_FIQ &&
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@ -464,7 +463,18 @@ static int aic_irq_domain_map(struct irq_domain *id, unsigned int irq,
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handle_fasteoi_irq, NULL, NULL);
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irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
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} else {
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irq_set_percpu_devid(irq);
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int fiq = hw - ic->nr_hw;
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switch (fiq) {
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case AIC_CPU_PMU_P:
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case AIC_CPU_PMU_E:
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irq_set_percpu_devid_partition(irq, &ic->fiq_aff[fiq]->aff);
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break;
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default:
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irq_set_percpu_devid(irq);
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break;
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}
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irq_domain_set_info(id, irq, hw, &fiq_chip, id->host_data,
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handle_percpu_devid_irq, NULL, NULL);
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}
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