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SoCFPGA DTS updates for v6.6 

- Fix dtbs_check warnings for usbphy, sram, rstmgr, memory, partitions
 - Updated "stmmaceth-ocp" reset-names to "ahb" for stmmac ethernet
 - Add initial support for Agilex5
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Merge tag 'socfpga_dts_updates_for_v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt

SoCFPGA DTS updates for v6.6
- Fix dtbs_check warnings for usbphy, sram, rstmgr, memory, partitions
- Updated "stmmaceth-ocp" reset-names to "ahb" for stmmac ethernet
- Add initial support for Agilex5

* tag 'socfpga_dts_updates_for_v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA
  dt-bindings: clock: add Intel Agilex5 clock manager
  dt-bindings: reset: add reset IDs for Agilex5
  dt-bindings: intel: Add Intel Agilex5 compatible
  arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb"
  arm64: dts: socfpga: n5x/stratix10: fix dtbs_check warning for partitions
  arm64: dts: agilex/stratix10: Updated QSPI Flash layout for UBIFS
  arm64: dts: agilex/stratix10/n5x: fix dtbs_check for rstmgr
  arm64: dts: stratix10/agilex/n5x: fix dtbs_check warning for memory node
  arm64: dts: socfpga: stratix10: fix dtbs_check warning for usbphy
  arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram

Link: https://lore.kernel.org/r/20230819161418.931258-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-08-21 21:48:48 -04:00
parent ecd2dc2f34 2d599bc438
commit c708140e96
17 changed files with 703 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/arm/intel,socfpga.yaml
View File

@ -21,6 +21,11 @@ properties:
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
- description: Agilex5 boards
items:
- enum:
- intel,socfpga-agilex5-socdk
- const: intel,socfpga-agilex5
additionalProperties: true

40
Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml Normal file
View File

@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA Agilex5 clock manager
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
description:
The Intel Agilex5 Clock Manager is an integrated clock controller, which
generates and supplies clock to all the modules.
properties:
compatible:
const: intel,agilex5-clkmgr
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clkmgr: clock-controller@10d10000 {
compatible = "intel,agilex5-clkmgr";
reg = <0x10d10000 0x1000>;
#clock-cells = <1>;
};
...

6
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
View File

@ -440,7 +440,7 @@
clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@ -460,7 +460,7 @@
clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@ -480,7 +480,7 @@
clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
clock-names = "stmmaceth", "ptp_ref";
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};

20
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@ -153,7 +153,7 @@
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
@ -171,7 +171,7 @@
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
@ -189,7 +189,7 @@
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
clock-names = "stmmaceth", "ptp_ref";
tx-fifo-depth = <16384>;
@ -331,6 +331,9 @@
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xffe00000 0x100000>;
};
pdma: dma-controller@ffda0000 {
@ -484,12 +487,6 @@
status = "disabled";
};
usbphy0: usbphy@0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
};
usb0: usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0x40000>;
@ -636,4 +633,9 @@
};
};
};
usbphy0: usbphy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};

12
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View File

@ -38,10 +38,10 @@
};
};
memory {
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x80000000 0 0>;
};
ref_033v: regulator-v-ref {
@ -202,12 +202,12 @@
qspi_boot: partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x03FE0000>;
reg = <0x0 0x04200000>;
};
qspi_rootfs: partition@3FE0000 {
label = "Root Filesystem - JFFS2";
reg = <0x03FE0000 0x0C020000>;
root: partition@4200000 {
label = "Root Filesystem - UBIFS";
reg = <0x04200000 0x0BE00000>;
};
};
};

8
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
View File

@ -38,10 +38,10 @@
};
};
memory {
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x80000000 0 0>;
};
ref_033v: regulator-v-ref {
@ -103,9 +103,9 @@
status = "okay";
flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
nand-bus-width = <16>;
partition@0 {
@ -194,7 +194,7 @@
reg = <0x0 0x03FE0000>;
};
qspi_rootfs: partition@3FE0000 {
qspi_rootfs: partition@3fe0000 {
label = "Root Filesystem - JFFS2";
reg = <0x03FE0000 0x0C020000>;
};

2
arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts
View File

@ -29,7 +29,7 @@
linux,initrd-end = <0x125c8324>;
};
memory {
memory@80000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};

1
arch/arm64/boot/dts/intel/Makefile
View File

@ -2,5 +2,6 @@
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_agilex5_socdk.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb

13
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View File

@ -158,7 +158,7 @@
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
@ -176,7 +176,7 @@
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
@ -194,7 +194,7 @@
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
reset-names = "stmmaceth", "stmmaceth-ocp";
reset-names = "stmmaceth", "ahb";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
snps,multicast-filter-bins = <256>;
@ -336,6 +336,9 @@
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xffe00000 0x40000>;
};
pdma: dma-controller@ffda0000 {
@ -373,9 +376,9 @@
};
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,stratix10-rst-mgr";
compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
reg = <0xffd11000 0x100>;
#reset-cells = <1>;
};
smmu: iommu@fa000000 {

468
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi Normal file
View File

@ -0,0 +1,468 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2023, Intel Corporation
*/
/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/intel,agilex5-clkmgr.h>
/ {
compatible = "intel,socfpga-agilex5";
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
service_reserved: svcbuffer@0 {
compatible = "shared-dma-pool";
reg = <0x0 0x80000000 0x0 0x2000000>;
alignment = <0x1000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a55";
reg = <0x100>;
device_type = "cpu";
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a76";
reg = <0x200>;
device_type = "cpu";
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a76";
reg = <0x300>;
device_type = "cpu";
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
intc: interrupt-controller@1d000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x1d000000 0 0x10000>,
<0x0 0x1d060000 0 0x100000>;
ranges;
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells =<2>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
its: msi-controller@1d040000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x1d040000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
};
/* Clock tree 5 main sources*/
clocks {
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
cb_intosc_ls_clk: cb-intosc-ls-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
f2s_free_clk: f2s-free-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
qspi_clk: qspi-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
usbphy0: usbphy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
};
soc: soc@0 {
compatible = "simple-bus";
ranges = <0 0 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
interrupt-parent = <&intc>;
clkmgr: clock-controller@10d10000 {
compatible = "intel,agilex5-clkmgr";
reg = <0x10d10000 0x1000>;
#clock-cells = <1>;
};
i2c0: i2c@10c02800 {
compatible = "snps,designware-i2c";
reg = <0x10c02800 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst I2C0_RESET>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
status = "disabled";
};
i2c1: i2c@10c02900 {
compatible = "snps,designware-i2c";
reg = <0x10c02900 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst I2C1_RESET>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
status = "disabled";
};
i2c2: i2c@10c02a00 {
compatible = "snps,designware-i2c";
reg = <0x10c02a00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst I2C2_RESET>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
status = "disabled";
};
i2c3: i2c@10c02b00 {
compatible = "snps,designware-i2c";
reg = <0x10c02b00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst I2C3_RESET>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
status = "disabled";
};
i2c4: i2c@10c02c00 {
compatible = "snps,designware-i2c";
reg = <0x10c02c00 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst I2C4_RESET>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
status = "disabled";
};
i3c0: i3c-master@10da0000 {
compatible = "snps,dw-i3c-master-1.00a";
reg = <0x10da0000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
status = "disabled";
};
i3c1: i3c-master@10da1000 {
compatible = "snps,dw-i3c-master-1.00a";
reg = <0x10da1000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
status = "disabled";
};
gpio1: gpio@10c03300 {
compatible = "snps,dw-apb-gpio";
reg = <0x10c03300 0x100>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst GPIO1_RESET>;
status = "disabled";
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
};
};
nand: nand-controller@10b80000 {
compatible = "cdns,hp-nfc";
reg = <0x10b80000 0x10000>,
<0x10840000 0x10000>;
reg-names = "reg", "sdma";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
cdns,board-delay-ps = <4830>;
status = "disabled";
};
ocram: sram@0 {
compatible = "mmio-sram";
reg = <0x00000000 0x80000>;
ranges = <0 0 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
};
dmac0: dma-controller@10db0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x10db0000 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
};
dmac1: dma-controller@10dc0000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x10dc0000 0x500>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
<&clkmgr AGILEX5_L4_MP_CLK>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <1>;
snps,data-width = <2>;
snps,block-size = <32767 32767 32767 32767>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <8>;
};
rst: rstmgr@10d11000 {
compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
reg = <0x10d11000 0x1000>;
#reset-cells = <1>;
};
spi0: spi@10da4000 {
compatible = "snps,dw-apb-ssi";
reg = <0x10da4000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst SPIM0_RESET>;
reset-names = "spi";
reg-io-width = <4>;
num-cs = <4>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
dmas = <&dmac0 2>, <&dmac0 3>;
dma-names ="tx", "rx";
status = "disabled";
};
spi1: spi@10da5000 {
compatible = "snps,dw-apb-ssi";
reg = <0x10da5000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst SPIM1_RESET>;
reset-names = "spi";
reg-io-width = <4>;
num-cs = <4>;
clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
status = "disabled";
};
sysmgr: sysmgr@10d12000 {
compatible = "altr,sys-mgr-s10","altr,sys-mgr";
reg = <0x10d12000 0x500>;
};
timer0: timer0@10c03000 {
compatible = "snps,dw-apb-timer";
reg = <0x10c03000 0x100>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
clock-names = "timer";
};
timer1: timer1@10c03100 {
compatible = "snps,dw-apb-timer";
reg = <0x10c03100 0x100>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
clock-names = "timer";
};
timer2: timer2@10d00000 {
compatible = "snps,dw-apb-timer";
reg = <0x10d00000 0x100>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
clock-names = "timer";
};
timer3: timer3@10d00100 {
compatible = "snps,dw-apb-timer";
reg = <0x10d00100 0x100>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
clock-names = "timer";
};
uart0: serial@10c02000 {
compatible = "snps,dw-apb-uart";
reg = <0x10c02000 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
status = "disabled";
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
};
uart1: serial@10c02100 {
compatible = "snps,dw-apb-uart";
reg = <0x10c02100 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst UART1_RESET>;
status = "disabled";
clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
};
usb0: usb@10b00000 {
compatible = "snps,dwc2";
reg = <0x10b00000 0x40000>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
clock-names = "otg";
status = "disabled";
};
watchdog0: watchdog@10d00200 {
compatible = "snps,dw-wdt";
reg = <0x10d00200 0x100>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst WATCHDOG0_RESET>;
clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
status = "disabled";
};
watchdog1: watchdog@10d00300 {
compatible = "snps,dw-wdt";
reg = <0x10d00300 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst WATCHDOG1_RESET>;
clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
status = "disabled";
};
watchdog2: watchdog@10d00400 {
compatible = "snps,dw-wdt";
reg = <0x10d00400 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst WATCHDOG2_RESET>;
clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
status = "disabled";
};
watchdog3: watchdog@10d00500 {
compatible = "snps,dw-wdt";
reg = <0x10d00500 0x100>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst WATCHDOG3_RESET>;
clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
status = "disabled";
};
watchdog4: watchdog@10d00600 {
compatible = "snps,dw-wdt";
reg = <0x10d00600 0x100>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst WATCHDOG4_RESET>;
clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
status = "disabled";
};
qspi: spi@108d2000 {
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
reg = <0x108d2000 0x100>,
<0x10900000 0x100000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
clocks = <&qspi_clk>;
status = "disabled";
};
};
};

39
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts Normal file
View File

@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2023, Intel Corporation
*/
#include "socfpga_agilex5.dtsi"
/ {
model = "SoCFPGA Agilex5 SoCDK";
compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&gpio1 {
status = "okay";
};
&osc1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};
&usb0 {
status = "okay";
disable-over-current;
};
&watchdog0 {
status = "okay";
};

4
arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
View File

@ -20,10 +20,10 @@
stdout-path = "serial0:115200n8";
};
memory@0 {
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x80000000 0 0>;
};
soc {

12
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
View File

@ -37,10 +37,10 @@
};
};
memory {
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x80000000 0 0>;
};
};
@ -128,12 +128,12 @@
qspi_boot: partition@0 {
label = "Boot and fpga data";
reg = <0x0 0x03FE0000>;
reg = <0x0 0x04200000>;
};
qspi_rootfs: partition@3FE0000 {
label = "Root Filesystem - JFFS2";
reg = <0x03FE0000 0x0C020000>;
root: partition@4200000 {
label = "Root Filesystem - UBIFS";
reg = <0x04200000 0x0BE00000>;
};
};
};

4
arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
View File

@ -37,10 +37,10 @@
};
};
memory {
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x80000000 0 0>;
};
};

6
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
View File

@ -19,10 +19,10 @@
stdout-path = "serial0:115200n8";
};
memory {
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x80000000 0 0>;
};
soc {
@ -109,7 +109,7 @@
reg = <0x0 0x03FE0000>;
};
qspi_rootfs: partition@3FE0000 {
qspi_rootfs: partition@3fe0000 {
label = "Root Filesystem - JFFS2";
reg = <0x03FE0000 0x0C020000>;
};

100
include/dt-bindings/clock/intel,agilex5-clkmgr.h Normal file
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@ -0,0 +1,100 @@
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright (C) 2023, Intel Corporation
*/
#ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
#define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
/* fixed rate clocks */
#define AGILEX5_OSC1 0
#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1
#define AGILEX5_CB_INTOSC_LS_CLK 2
#define AGILEX5_F2S_FREE_CLK 3
/* PLL clocks */
#define AGILEX5_MAIN_PLL_CLK 4
#define AGILEX5_MAIN_PLL_C0_CLK 5
#define AGILEX5_MAIN_PLL_C1_CLK 6
#define AGILEX5_MAIN_PLL_C2_CLK 7
#define AGILEX5_MAIN_PLL_C3_CLK 8
#define AGILEX5_PERIPH_PLL_CLK 9
#define AGILEX5_PERIPH_PLL_C0_CLK 10
#define AGILEX5_PERIPH_PLL_C1_CLK 11
#define AGILEX5_PERIPH_PLL_C2_CLK 12
#define AGILEX5_PERIPH_PLL_C3_CLK 13
#define AGILEX5_CORE0_FREE_CLK 14
#define AGILEX5_CORE1_FREE_CLK 15
#define AGILEX5_CORE2_FREE_CLK 16
#define AGILEX5_CORE3_FREE_CLK 17
#define AGILEX5_DSU_FREE_CLK 18
#define AGILEX5_BOOT_CLK 19
/* fixed factor clocks */
#define AGILEX5_L3_MAIN_FREE_CLK 20
#define AGILEX5_NOC_FREE_CLK 21
#define AGILEX5_S2F_USR0_CLK 22
#define AGILEX5_NOC_CLK 23
#define AGILEX5_EMAC_A_FREE_CLK 24
#define AGILEX5_EMAC_B_FREE_CLK 25
#define AGILEX5_EMAC_PTP_FREE_CLK 26
#define AGILEX5_GPIO_DB_FREE_CLK 27
#define AGILEX5_S2F_USER0_FREE_CLK 28
#define AGILEX5_S2F_USER1_FREE_CLK 29
#define AGILEX5_PSI_REF_FREE_CLK 30
#define AGILEX5_USB31_FREE_CLK 31
/* Gate clocks */
#define AGILEX5_CORE0_CLK 32
#define AGILEX5_CORE1_CLK 33
#define AGILEX5_CORE2_CLK 34
#define AGILEX5_CORE3_CLK 35
#define AGILEX5_MPU_CLK 36
#define AGILEX5_MPU_PERIPH_CLK 37
#define AGILEX5_MPU_CCU_CLK 38
#define AGILEX5_L4_MAIN_CLK 39
#define AGILEX5_L4_MP_CLK 40
#define AGILEX5_L4_SYS_FREE_CLK 41
#define AGILEX5_L4_SP_CLK 42
#define AGILEX5_CS_AT_CLK 43
#define AGILEX5_CS_TRACE_CLK 44
#define AGILEX5_CS_PDBG_CLK 45
#define AGILEX5_EMAC1_CLK 47
#define AGILEX5_EMAC2_CLK 48
#define AGILEX5_EMAC_PTP_CLK 49
#define AGILEX5_GPIO_DB_CLK 50
#define AGILEX5_S2F_USER0_CLK 51
#define AGILEX5_S2F_USER1_CLK 52
#define AGILEX5_PSI_REF_CLK 53
#define AGILEX5_USB31_SUSPEND_CLK 54
#define AGILEX5_EMAC0_CLK 46
#define AGILEX5_USB31_BUS_CLK_EARLY 55
#define AGILEX5_USB2OTG_HCLK 56
#define AGILEX5_SPIM_0_CLK 57
#define AGILEX5_SPIM_1_CLK 58
#define AGILEX5_SPIS_0_CLK 59
#define AGILEX5_SPIS_1_CLK 60
#define AGILEX5_DMA_CORE_CLK 61
#define AGILEX5_DMA_HS_CLK 62
#define AGILEX5_I3C_0_CORE_CLK 63
#define AGILEX5_I3C_1_CORE_CLK 64
#define AGILEX5_I2C_0_PCLK 65
#define AGILEX5_I2C_1_PCLK 66
#define AGILEX5_I2C_EMAC0_PCLK 67
#define AGILEX5_I2C_EMAC1_PCLK 68
#define AGILEX5_I2C_EMAC2_PCLK 69
#define AGILEX5_UART_0_PCLK 70
#define AGILEX5_UART_1_PCLK 71
#define AGILEX5_SPTIMER_0_PCLK 72
#define AGILEX5_SPTIMER_1_PCLK 73
#define AGILEX5_DFI_CLK 74
#define AGILEX5_NAND_NF_CLK 75
#define AGILEX5_NAND_BCH_CLK 76
#define AGILEX5_SDMMC_SDPHY_REG_CLK 77
#define AGILEX5_SDMCLK 78
#define AGILEX5_SOFTPHY_REG_PCLK 79
#define AGILEX5_SOFTPHY_PHY_CLK 80
#define AGILEX5_SOFTPHY_CTRL_CLK 81
#define AGILEX5_NUM_CLKS 82
#endif /* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */

5
include/dt-bindings/reset/altr,rst-mgr-s10.h
View File

@ -63,12 +63,15 @@
#define I2C2_RESET 74
#define I2C3_RESET 75
#define I2C4_RESET 76
/* 77-79 is empty */
#define I3C0_RESET 77
#define I3C1_RESET 78
/* 79 is empty */
#define UART0_RESET 80
#define UART1_RESET 81
/* 82-87 is empty */
#define GPIO0_RESET 88
#define GPIO1_RESET 89
#define WATCHDOG4_RESET 90
/* BRGMODRST */
#define SOC2FPGA_RESET 96