arm64: dts: Add BRCM IPROC NAND DT node for NS2
The NAND controller on NS2 SoC is compatible with existing BRCM IPROC NAND driver so let's enable it in NS2 DT and NS2 SVK DT. This patch also fixes use of node labels in ns2-svk.dts. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Reviewed-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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@ -50,18 +50,28 @@
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device_type = "memory";
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reg = <0x000000000 0x80000000 0x00000000 0x40000000>;
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};
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};
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soc: soc {
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i2c0: i2c@66080000 {
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status = "ok";
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};
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&i2c0 {
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status = "ok";
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};
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i2c1: i2c@660b0000 {
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status = "ok";
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};
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&i2c1 {
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status = "ok";
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};
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uart3: serial@66130000 {
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status = "ok";
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};
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&uart3 {
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status = "ok";
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};
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&nand {
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nandcs@0 {
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compatible = "brcm,nandcs";
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reg = <0>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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@ -212,5 +212,19 @@
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compatible = "brcm,iproc-rng200";
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reg = <0x66220000 0x28>;
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};
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nand: nand@66460000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x66460000 0x600>,
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<0x67015408 0x600>,
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<0x66460f00 0x20>;
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reg-names = "nand", "iproc-idm", "iproc-ext";
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interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,nand-has-wp;
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};
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};
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};
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