tg3: Whitespace, constant, and comment updates
This patch fixes whitespace errors, preprocessor definition placement oddities and updates comments. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
184b89044f
commit
c6cdf43631
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@ -101,7 +101,7 @@
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#define TG3_DEF_RX_RING_PENDING 200
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#define TG3_RX_JUMBO_RING_SIZE 256
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#define TG3_DEF_RX_JUMBO_RING_PENDING 100
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#define TG3_RSS_INDIR_TBL_SIZE 128
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#define TG3_RSS_INDIR_TBL_SIZE 128
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/* Do not place this n-ring entries value into the tp struct itself,
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* we really want to expose these constants to GCC so that modulo et
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@ -142,6 +142,8 @@
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#define TG3_RX_JMB_BUFF_RING_SIZE \
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(sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
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#define TG3_RSS_MIN_NUM_MSIX_VECS 2
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/* minimum number of free TX descriptors required to wake up TX process */
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#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
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@ -152,6 +154,8 @@
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#define TG3_NUM_TEST 6
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#define TG3_FW_UPDATE_TIMEOUT_SEC 5
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#define FIRMWARE_TG3 "tigon/tg3.bin"
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#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
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#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
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@ -167,8 +171,6 @@ MODULE_FIRMWARE(FIRMWARE_TG3);
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MODULE_FIRMWARE(FIRMWARE_TG3TSO);
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MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
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#define TG3_RSS_MIN_NUM_MSIX_VECS 2
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static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
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module_param(tg3_debug, int, 0);
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MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
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@ -496,16 +498,16 @@ static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
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writel(val, tp->regs + off + GRCMBOX_BASE);
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}
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#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
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#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
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#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
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#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
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#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
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#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
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#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
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#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
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#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
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#define tw32(reg,val) tp->write32(tp, reg, val)
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#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
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#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
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#define tr32(reg) tp->read32(tp, reg)
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#define tw32(reg, val) tp->write32(tp, reg, val)
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#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
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#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
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#define tr32(reg) tp->read32(tp, reg)
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static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
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{
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@ -651,6 +653,7 @@ static void tg3_enable_ints(struct tg3 *tp)
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tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
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for (i = 0; i < tp->irq_cnt; i++) {
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struct tg3_napi *tnapi = &tp->napi[i];
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tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
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if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
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tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
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@ -1437,7 +1440,7 @@ static void tg3_adjust_link(struct net_device *dev)
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phydev->speed != tp->link_config.active_speed ||
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phydev->duplex != tp->link_config.active_duplex ||
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oldflowctrl != tp->link_config.active_flowctrl)
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linkmesg = 1;
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linkmesg = 1;
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tp->link_config.active_speed = phydev->speed;
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tp->link_config.active_duplex = phydev->duplex;
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@ -2007,8 +2010,8 @@ out:
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u32 phy_reg;
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if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
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tg3_writephy(tp, MII_TG3_EXT_CTRL,
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phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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@ -4211,6 +4214,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
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tp->serdes_counter--;
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return;
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}
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if (!netif_carrier_ok(tp->dev) &&
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(tp->link_config.autoneg == AUTONEG_ENABLE)) {
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u32 bmcr;
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@ -4519,8 +4523,8 @@ static void tg3_recycle_rx(struct tg3_napi *tnapi,
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struct tg3 *tp = tnapi->tp;
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struct tg3_rx_buffer_desc *src_desc, *dest_desc;
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struct ring_info *src_map, *dest_map;
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int dest_idx;
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struct tg3_rx_prodring_set *spr = &tp->prodring[0];
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int dest_idx;
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switch (opaque_key) {
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case RXD_OPAQUE_RING_STD:
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@ -4981,7 +4985,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
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if (unlikely(work_done >= budget))
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break;
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/* tp->last_tag is used in tg3_restart_ints() below
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/* tp->last_tag is used in tg3_int_reenable() below
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* to tell the hw how much work has been processed,
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* so we must read it before checking for more work.
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*/
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@ -5496,7 +5500,6 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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struct netdev_queue *txq;
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unsigned int i, last;
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txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
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tnapi = &tp->napi[skb_get_queue_mapping(skb)];
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if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
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@ -5700,7 +5703,6 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
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struct netdev_queue *txq;
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unsigned int i, last;
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txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
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tnapi = &tp->napi[skb_get_queue_mapping(skb)];
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if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
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@ -6013,7 +6015,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
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}
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}
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/* Initialize tx/rx rings for packet processing.
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/* Initialize rx rings for packet processing.
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*
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* The chip has been shut down and the driver detached from
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* the networking, so no interrupts or new tx packets will
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@ -8491,8 +8493,8 @@ static void tg3_timer(unsigned long __opaque)
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
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FWCMD_NICDRV_ALIVE3);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
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/* 5 seconds timeout */
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
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tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
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TG3_FW_UPDATE_TIMEOUT_SEC);
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tg3_generate_fw_event(tp);
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}
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@ -9634,7 +9636,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
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memcpy(data, ((char*)&val) + b_offset, b_count);
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len -= b_count;
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offset += b_count;
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eeprom->len += b_count;
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eeprom->len += b_count;
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}
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/* read bytes upto the last 4 byte boundary */
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@ -10182,8 +10184,8 @@ static int tg3_set_rx_csum(struct net_device *dev, u32 data)
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if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
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if (data != 0)
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return -EINVAL;
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return 0;
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}
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return 0;
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}
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spin_lock_bh(&tp->lock);
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if (data)
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@ -10202,8 +10204,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
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if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
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if (data != 0)
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return -EINVAL;
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return 0;
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}
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return 0;
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}
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if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
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ethtool_op_set_tx_ipv6_csum(dev, data);
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@ -10477,7 +10479,7 @@ static int tg3_test_registers(struct tg3 *tp)
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{ MAC_ADDR_0_HIGH, 0x0000,
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0x00000000, 0x0000ffff },
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{ MAC_ADDR_0_LOW, 0x0000,
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0x00000000, 0xffffffff },
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0x00000000, 0xffffffff },
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{ MAC_RX_MTU_SIZE, 0x0000,
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0x00000000, 0x0000ffff },
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{ MAC_TX_MODE, 0x0000,
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@ -11913,7 +11915,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
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if (ret)
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break;
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page_off = offset & pagemask;
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page_off = offset & pagemask;
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size = pagesize;
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if (len < size)
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size = len;
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@ -11941,7 +11943,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
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NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
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if (tg3_nvram_exec_cmd(tp, nvram_cmd))
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if (tg3_nvram_exec_cmd(tp, nvram_cmd))
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break;
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/* Issue another write enable to start the write. */
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@ -11995,7 +11997,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
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memcpy(&data, buf + i, 4);
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tw32(NVRAM_WRDATA, be32_to_cpu(data));
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page_off = offset % tp->nvram_pagesize;
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page_off = offset % tp->nvram_pagesize;
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phy_addr = tg3_nvram_phys_addr(tp, offset);
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@ -12003,7 +12005,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
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if ((page_off == 0) || (i == 0))
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if (page_off == 0 || i == 0)
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nvram_cmd |= NVRAM_CMD_FIRST;
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if (page_off == (tp->nvram_pagesize - 4))
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nvram_cmd |= NVRAM_CMD_LAST;
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@ -12949,9 +12951,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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{
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static struct pci_device_id write_reorder_chipsets[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_FE_GATE_700C) },
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PCI_DEVICE_ID_AMD_FE_GATE_700C) },
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_8131_BRIDGE) },
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PCI_DEVICE_ID_AMD_8131_BRIDGE) },
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{ PCI_DEVICE(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_8385_0) },
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{ },
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@ -13240,8 +13242,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
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(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
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(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
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tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
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pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
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@ -23,7 +23,7 @@
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#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
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#define TG3_BDINFO_SIZE 0x10UL
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#define RX_COPY_THRESHOLD 256
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#define RX_COPY_THRESHOLD 256
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#define TG3_RX_INTERNAL_RING_SZ_5906 32
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@ -252,7 +252,7 @@
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/* 0x94 --> 0x98 unused */
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#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
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#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
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/* 0xa0 --> 0xb8 unused */
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/* 0xa8 --> 0xb8 unused */
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#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
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#define DUAL_MAC_CTRL_CH_MASK 0x00000003
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#define DUAL_MAC_CTRL_ID 0x00000004
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@ -2561,7 +2561,7 @@ struct tg3_bufmgr_config {
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struct tg3_ethtool_stats {
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/* Statistics maintained by Receive MAC. */
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u64 rx_octets;
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u64 rx_octets;
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u64 rx_fragments;
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u64 rx_ucast_packets;
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u64 rx_mcast_packets;
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